/*	$Id: cp7000.h,v 1.5 2002/08/13 23:02:27 mdharm Exp $ */

/*
 * Copyright (c) 2000 Opsycon AB  (www.opsycon.se)
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed by
 *	Opsycon Open System Consulting AB, Sweden.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */

#ifndef _EV64120_H_
#define _EV64120_H_

#include <machine/endian.h>

/*
 *  GT64120 config space base address
 */
#define	GT64120_BASE	0xf4000000

/*
 *  PCI Bus allocation
 */
#define	PCI0_MEM_SPACE_BASE	0xe0000000
#define	PCI0_MEM_SPACE_SIZE	0x08000000
#define	PCI0_IO_SPACE_BASE	0xe8000000
#define	PCI0_IO_SPACE_SIZE	0x08000000

/*
 *  I/O address block location.
 */
#define	IO_BLOCK_START		0xfc000000	/* Default is 1c000000 */
#define	IO_BLOCK_END		0xfe1fffff	/* Default is 1e1fffff */

#define	IO_BASE			PHYS_TO_UNCACHED(IO_BLOCK_START)
#define PLD_BASE_ADDR 		(IO_BASE + 0x00000000)	/* CS0 */
#define	NVRAM_BASE_ADDR		(IO_BASE + 0x00800000)	/* CS1 */
#define COM_BASE_ADDRESS	(IO_BASE + 0x01000000)	/* CS2 */

/*
 *  Boot and CS3 block location.
 */
#define	BOOT_BLOCK_START	0xff000000	/* Default is 1f000000 */
#define	BOOT_BLOCK_END		0xffffffff	/* Default is 1fffffff */

/*
 *  Timekeeper/NVRAM (M48T37)
 */
#define	NVRAM_SIZE		(0x7ff0)
#define	NVRAM_BASE		NVRAM_BASE_ADDR
#define NVRAM_FIRST_ENV         (NVRAM_BASE + 0x0000)
#define NVRAM_LAST_ENV          (NVRAM_BASE + 0x77ff)
#define NVRAM_SIZE_ENV          (NVRAM_LAST_ENV - NVRAM_FIRST_ENV + 1)
#define NVRAM_VXWORKS           (NVRAM_BASE + NVRAM_SIZE - 512)
#define NVRAM_VXWORKS_DEFAULT \
"dc(0,0)host:/usr/vw/config/cp7000/vxWorks h=90.0.0.3 e=90.0.0.50 u=target"
#define NVRAM_ENETADDR          (NVRAM_BASE + 0x7cf2)

#define	M48T37_BASE		(NVRAM_BASE_ADDR + NVRAM_SIZE)

/*
 *  Duart I/O ports.
 */
#define COM1_BASE_ADDR	(COM_BASE_ADDRESS + 0x0020)	/* Com 1 */
#define COM2_BASE_ADDR	(COM_BASE_ADDRESS + 0x0000)	/* Com 2 */
#define	NS16550HZ	20000000
#if BYTE_ORDER == LITTLE_ENDIAN
#define nsreg(x) unsigned char CAT(pad_,x)[3]; unsigned char x;
#define	NSREG(x) ((x) * 4 + 3)
#endif
#if BYTE_ORDER == BIG_ENDIAN
#define nsreg(x) unsigned char x;unsigned char CAT(pad_,x)[3];
#define	NSREG(x) ((x) * 4)
#endif

/*
 * PLD Address
 */
#define	PLD_BAR		(PLD_BASE_ADDR + 0x00)
#define	PLD_ID1		(PLD_BASE_ADDR + 0x01)
#define	PLD_ID2		(PLD_BASE_ADDR + 0x02)
#define	PLD_RSTAT	(PLD_BASE_ADDR + 0x03)
#define	PLD_BSTAT	(PLD_BASE_ADDR + 0x04)
#define	PLD_CPCI	(PLD_BASE_ADDR + 0x05)

/* Some default values */
#define GT_SDRAM_BANK0_PARAM	0x00000C69

#endif