/* * Copyright (c) 2004 PMC-Sierra, Inc. (www.pmc-sierra.com) * Author: brad_larson@pmc-sierra.com * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Opsycon AB. * 4. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #if !defined(_RM9000_MAC_H_) #define _RM9000_MAC_H_ /* * MAC subsytem registers */ /* MAC Subsystem */ #define RM9000_GE_DEVICE_ID_REG 0x0000 #define RM9000_GE_RESET 0x0004 #define RM9000_GE_DLL_STATUS 0x0008 #define RM9000_TSB_CONTROL_0 0x000c #define RM9000_TSB_CONTROL_1 0x0010 #define RM9000_PRIORITY_CHECKSUM_PORT_0 0x1038 #define RM9000_PRIORITY_CHECKSUM_PORT_1 0x2038 #define RM9000_PRIORITY_CHECKSUM_PORT_2 0x3038 /* L1TPP */ #define RM9000_L1TPP_CONFIG_PORT_0 0x1300 #define RM9000_L1TPP_CONFIG_PORT_1 0x2300 #define RM9000_L1TPP_CONFIG_PORT_2 0x3300 /* L1RPP */ #define RM9000_L1RPP_CONFIG_PORT_0 0x128c #define RM9000_L1RPP_CONFIG_PORT_1 0x228c #define RM9000_L1RPP_CONFIG_PORT_2 0x328c #define RM9000_L1RPP_INTERRUPT_PORT_0 0x1280 #define RM9000_L1RPP_INTERRUPT_PORT_1 0x2280 #define RM9000_L1RPP_INTERRUPT_PORT_2 0x3280 #define RM9000_L1RPP_INTERRUPT_ENABLE_PORT_0 0x1284 #define RM9000_L1RPP_INTERRUPT_ENABLE_PORT_1 0x2284 #define RM9000_L1RPP_INTERRUPT_ENABLE_PORT_2 0x3284 #define RM9000_L1RPP_INTERRUPT_STATUS_PORT_0 0x1288 #define RM9000_L1RPP_INTERRUPT_STATUS_PORT_1 0x2288 #define RM9000_L1RPP_INTERRUPT_STATUS_PORT_2 0x3288 #define RM9000_L1RPP_JITTER_STATUS_PORT_0 0x1294 #define RM9000_L1RPP_JITTER_STATUS_PORT_1 0x2294 #define RM9000_L1RPP_JITTER_STATUS_PORT_2 0x3294 #define RM9000_L1RPP_MII_CONTROL_PORT_0 0x1298 #define RM9000_L1RPP_MII_CONTROL_PORT_1 0x2298 #define RM9000_L1RPP_MII_CONTROL_PORT_2 0x3298 #define RM9000_L1RPP_MII_STATUS_PORT_0 0x129c #define RM9000_L1RPP_MII_STATUS_PORT_1 0x229c #define RM9000_L1RPP_MII_STATUS_PORT_2 0x329c #define RM9000_L1RPP_MII_AUTONEG_PORT_0 0x12a0 #define RM9000_L1RPP_MII_AUTONEG_PORT_1 0x22a0 #define RM9000_L1RPP_MII_AUTONEG_PORT_2 0x32a0 /* Flow Control */ #define RM9000_GE_FC_NONE 0x0 #define RM9000_GE_FC_FULL 0x1 #define RM9000_GE_FC_TX_PAUSE 0x2 #define RM9000_GE_FC_RX_PAUSE 0x3 /* Duplex Settings */ #define RM9000_GE_FULL_DUPLEX 0x1 #define RM9000_GE_HALF_DUPLEX 0x2 /* Speed settings */ #define RM9000_GE_SPEED_1000 0x1 #define RM9000_GE_SPEED_100 0x2 #define RM9000_GE_SPEED_10 0x3 /* Default Tx Queue Size */ #define RM9000_GE_TX_QUEUE 100 /* Default Rx Queue Size */ #define RM9000_GE_RX_QUEUE 80 /* Tx and Rx Interrupt Coalescing */ #define RM9000_GE_RX_COAL 200 #define RM9000_GE_TX_COAL 200 /* Rx MAC defines */ #define RM9000_GE_RMAC_CONFIG_1_PORT_0 0x1200 /* RMAC Configuration 1 Port 0 */ #define RM9000_GE_RMAC_CONFIG_1_PORT_1 0x2200 /* RMAC Configuration 1 Port 1 */ #define RM9000_GE_RMAC_CONFIG_1_PORT_2 0x3200 /* RMAC Configuration 1 Port 2 */ #define RM9000_GE_RMAC_CONFIG_2_PORT_0 0x1204 /* RMAC Configuration 2 Port 0 */ #define RM9000_GE_RMAC_CONFIG_2_PORT_1 0x2204 /* RMAC Configuration 2 Port 1 */ #define RM9000_GE_RMAC_CONFIG_2_PORT_2 0x3204 /* RMAC Configuration 2 Port 2 */ #define RM9000_GE_RMAC_MAX_FRAME_LEN 0x1208 /* RMAC Max Frame Length */ #define RM9000_GE_RMAC_STATION_HI 0x120C /* Rx Station Address High */ #define RM9000_GE_RMAC_STATION_MID 0x1210 /* Rx Station Address Middle */ #define RM9000_GE_RMAC_STATION_LOW 0x1214 /* Rx Station Address Low */ #define RM9000_GE_RMAC_LINK_CONFIG_PORT_0 0x1218 /* RMAC Link Configuration Port 0 */ #define RM9000_GE_RMAC_LINK_CONFIG_PORT_1 0x2218 /* RMAC Link Configuration Port 1 */ #define RM9000_GE_RMAC_LINK_CONFIG_PORT_2 0x3218 /* RMAC Link Configuration Port 2 */ /* Tx MAC defines */ #define RM9000_GE_TMAC_CONFIG_1_PORT_0 0x1240 /* TMAC Configuration 1 */ #define RM9000_GE_TMAC_CONFIG_1_PORT_1 0x2240 /* TMAC Configuration 1 */ #define RM9000_GE_TMAC_CONFIG_1_PORT_2 0x3240 /* TMAC Configuration 1 */ #define RM9000_GE_TMAC_CONFIG_2_PORT_0 0x1244 /* TMAC Configuration 2 */ #define RM9000_GE_TMAC_CONFIG_2_PORT_1 0x2244 /* TMAC Configuration 2 */ #define RM9000_GE_TMAC_CONFIG_2_PORT_2 0x3244 /* TMAC Configuration 2 */ #define RM9000_GE_TMAC_IPG 0x1248 /* TMAC Inter-Packet Gap */ #define RM9000_GE_TMAC_STATION_HI 0x124C /* Tx Station Address High */ #define RM9000_GE_TMAC_STATION_MID 0x1250 /* Tx Station Address Middle */ #define RM9000_GE_TMAC_STATION_LOW 0x1254 /* Tx Station Address Low */ #define RM9000_GE_TMAC_MAX_FRAME_LEN 0x1258 /* TMAC Max Frame Length */ #define RM9000_GE_TMAC_MIN_FRAME_LEN 0x125C /* TMAC Min Frame Length */ #define RM9000_GE_TMAC_PAUSE_FRAME_TIME 0x1260 /* TMAC Pause Frame Time */ #define RM9000_GE_TMAC_PAUSE_FRAME_INTERVAL 0x1264 /* TMAC Pause Frame Interval */ /* GMII register */ #define RM9000_GE_GMII_CONFIG_GENERAL_PORT_0 0x134C /* GMII Configuration General Port 0 */ #define RM9000_GE_GMII_CONFIG_GENERAL_PORT_1 0x234C /* GMII Configuration General Port 1 */ #define RM9000_GE_GMII_CONFIG_GENERAL_PORT_2 0x334C /* GMII Configuration General Port 2 */ #define RM9000_GE_GMII_CONFIG_MODE_PORT_0 0x1350 /* GMII Configuration Mode Port 0 */ #define RM9000_GE_GMII_CONFIG_MODE_PORT_1 0x2350 /* GMII Configuration Mode Port 1 */ #define RM9000_GE_GMII_CONFIG_MODE_PORT_2 0x3350 /* GMII Configuration Mode Port 2 */ #define RM9000_GE_GMII_INTERRUPT_PORT_0 0x1340 /* GMII Interrupt Port 0 */ #define RM9000_GE_GMII_INTERRUPT_PORT_1 0x2340 /* GMII Interrupt Port 1 */ #define RM9000_GE_GMII_INTERRUPT_PORT_2 0x3340 /* GMII Interrupt Port 2 */ #define RM9000_GE_GMII_INTERRUPT_STATUS_PORT_0 0x1348 /* GMII Interrupt Status 0 */ #define RM9000_GE_GMII_INTERRUPT_STATUS_PORT_1 0x2348 /* GMII Interrupt Status 1 */ #define RM9000_GE_GMII_INTERRUPT_STATUS_PORT_2 0x3348 /* GMII Interrupt Status 2 */ /* Interrupt Mapping to CIC */ #define RM9000_INT_CONFIG_0 0x0020 /* Interrupt config register 0 */ #define RM9000_INT_CONFIG_1 0x0024 /* Interrupt config register 1 */ #define RM9000_XDMA_INT_STATUS_A 0x0048 /* XDMA Interrupt Status A */ #define RM9000_XDMA_INT_STATUS_B 0x004c /* XDMA Interrupt Status B */ /* Tx and Rx XDMA defines */ #define RM9000_XDMA_CONFIG 0x5000 /* XDMA configuration */ #define RM9000_INTERRUPT_COALESCING 0x5030 /* Interrupt coalescing */ #define RM9000_XDMA_BUFFER_PREFIX 0x5018 /* Tx/Rx XDMA buffer prefix */ #define RM9000_XDMA_DESCRIPTOR_PREFIX 0x501c /* Tx/Rx XDMA descriptor prefix */ /* XDMA Channel 0 */ #define RM9000_XDMA_CHANNEL0_CONFIG 0x5040 /* Channel 0 XDMA config */ #define RM9000_XDMA_CHANNEL0_TX_DMA_STATUS 0x5044 /* Channel 0 Transmit DMA status */ #define RM9000_XDMA_CHANNEL0_RX_DMA_STATUS 0x5048 /* Channel 0 Receive DMA status */ #define RM9000_XDMA_CHANNEL0_INTERRUPT 0x504c /* Channel 0 Interrupt Status */ #define RM9000_XDMA_CHANNEL0_INTERRUPT_ENABLE 0x5050 /* Channel 0 Interrupt enable */ #define RM9000_XDMA_CHANNEL0_TX_DESC 0x5054 /* Channel 0 Tx first desc */ #define RM9000_XDMA_CHANNEL0_RX_DESC 0x5058 /* Channel 0 Rx first desc */ #define RM9000_XDMA_CHANNEL0_PACKET_COUNT 0x5060 /* Channel 0 Packet count */ #define RM9000_XDMA_CHANNEL0_BYTE_COUNT 0x5064 /* Channel 0 Byte count */ /* XDMA Channel 1 */ #define RM9000_XDMA_CHANNEL1_CONFIG 0x5080 /* Channel 1 XDMA config */ #define RM9000_XDMA_CHANNEL1_TX_DMA_STATUS 0x5084 /* Channel 1 Transmit DMA status */ #define RM9000_XDMA_CHANNEL1_RX_DMA_STATUS 0x5088 /* Channel 1 Receive DMA status */ #define RM9000_XDMA_CHANNEL1_INTERRUPT 0x508c /* Channel 1 Interrupt Status */ #define RM9000_XDMA_CHANNEL1_INTERRUPT_ENABLE 0x5090 /* Channel 1 Interrupt enable */ #define RM9000_XDMA_CHANNEL1_TX_DESC 0x5094 /* Channel 1 Tx first desc */ #define RM9000_XDMA_CHANNEL1_RX_DESC 0x5098 /* Channel 1 Rx first desc */ #define RM9000_XDMA_CHANNEL1_PACKET_COUNT 0x50a0 /* Channel 1 Packet count */ #define RM9000_XDMA_CHANNEL1_BYTE_COUNT 0x50a4 /* Channel 1 Byte count */ /* XDMA Channel 2 */ #define RM9000_XDMA_CHANNEL2_CONFIG 0x50c0 /* Channel 2 XDMA config */ #define RM9000_XDMA_CHANNEL2_TX_DMA_STATUS 0x50c4 /* Channel 2 Transmit DMA status */ #define RM9000_XDMA_CHANNEL2_RX_DMA_STATUS 0x50c8 /* Channel 2 Receive DMA status */ #define RM9000_XDMA_CHANNEL2_INTERRUPT 0x50cc /* Channel 2 Interrupt Status */ #define RM9000_XDMA_CHANNEL2_INTERRUPT_ENABLE 0x50d0 /* Channel 2 Interrupt enable */ #define RM9000_XDMA_CHANNEL2_TX_DESC 0x50d4 /* Channel 2 Tx first desc */ #define RM9000_XDMA_CHANNEL2_RX_DESC 0x50d8 /* Channel 2 Rx first desc */ #define RM9000_XDMA_CHANNEL2_PACKET_COUNT 0x50e0 /* Channel 2 Packet count */ #define RM9000_XDMA_CHANNEL2_BYTE_COUNT 0x50e4 /* Channel 2 Byte count */ /* XDMA Channel 4 */ #define RM9000_XDMA_CHANNEL4_CONFIG 0x5140 /* Channel 4 XDMA config */ #define RM9000_XDMA_CHANNEL4_TX_DMA_STATUS 0x5144 /* Channel 4 Transmit DMA status */ #define RM9000_XDMA_CHANNEL4_RX_DMA_STATUS 0x5148 /* Channel 4 Receive DMA status */ #define RM9000_XDMA_CHANNEL4_INTERRUPT 0x514c /* Channel 4 Interrupt Status */ #define RM9000_XDMA_CHANNEL4_INTERRUPT_ENABLE 0x5150 /* Channel 4 Interrupt enable */ #define RM9000_XDMA_CHANNEL4_TX_DESC 0x5154 /* Channel 4 Tx first desc */ #define RM9000_XDMA_CHANNEL4_RX_DESC 0x5158 /* Channel 4 Rx first desc */ #define RM9000_XDMA_CHANNEL4_PACKET_COUNT 0x5160 /* Channel 4 Packet count */ #define RM9000_XDMA_CHANNEL4_BYTE_COUNT 0x5164 /* Channel 4 Byte count */ /* XDMA Channel 8 */ #define RM9000_XDMA_CHANNEL8_CONFIG 0x5240 /* Channel 8 XDMA config */ #define RM9000_XDMA_CHANNEL8_TX_DMA_STATUS 0x5244 /* Channel 8 Transmit DMA status */ #define RM9000_XDMA_CHANNEL8_RX_DMA_STATUS 0x5248 /* Channel 8 Receive DMA status */ #define RM9000_XDMA_CHANNEL8_INTERRUPT 0x524c /* Channel 8 Interrupt Status */ #define RM9000_XDMA_CHANNEL8_INTERRUPT_ENABLE 0x5250 /* Channel 8 Interrupt enable */ #define RM9000_XDMA_CHANNEL8_TX_DESC 0x5254 /* Channel 8 Tx first desc */ #define RM9000_XDMA_CHANNEL8_RX_DESC 0x5258 /* Channel 8 Rx first desc */ #define RM9000_XDMA_CHANNEL8_PACKET_COUNT 0x5260 /* Channel 8 Packet count */ #define RM9000_XDMA_CHANNEL8_BYTE_COUNT 0x5264 /* Channel 8 Byte count */ /* Packet FIFO */ #define RM9000_RX_FIFO_CONTROL 0x4828 /* Rx FIFO control */ #define RM9000_TX_FIFO_CONTROL 0x4928 /* Tx FIFO control */ #define RM9000_RX_FIFO_0_CONFIG 0x4840 /* Rx FIFO 0 config */ #define RM9000_RX_FIFO_1_CONFIG 0x484c /* Rx FIFO 1 config */ #define RM9000_RX_FIFO_2_CONFIG 0x4858 /* Rx FIFO 2 config */ #define RM9000_RX_FIFO_3_CONFIG 0x4864 /* Rx FIFO 3 config */ #define RM9000_RX_FIFO_4_CONFIG 0x4870 /* Rx FIFO 4 config */ #define RM9000_RX_FIFO_5_CONFIG 0x487c /* Rx FIFO 5 config */ #define RM9000_RX_FIFO_6_CONFIG 0x4888 /* Rx FIFO 6 config */ #define RM9000_RX_FIFO_7_CONFIG 0x4894 /* Rx FIFO 7 config */ #define RM9000_RX_FIFO_8_CONFIG 0x48a0 /* Rx FIFO 8 config */ #define RM9000_RX_FIFO_9_CONFIG 0x48ac /* Rx FIFO 9 config */ #define RM9000_RX_FIFO_10_CONFIG 0x48b8 /* Rx FIFO 10 config */ #define RM9000_RX_FIFO_11_CONFIG 0x48c4 /* Rx FIFO 11 config */ #define RM9000_TX_FIFO_0_CONFIG 0x4940 /* Tx FIFO 0 config */ #define RM9000_TX_FIFO_1_CONFIG 0x494c /* Tx FIFO 1 config */ #define RM9000_TX_FIFO_2_CONFIG 0x4958 /* Tx FIFO 2 config */ #define RM9000_RX_FIFO_0_THRESHOLD 0x4844 /* Rx FIFO 0 threshold */ #define RM9000_RX_FIFO_1_THRESHOLD 0x4850 /* Rx FIFO 1 threshold */ #define RM9000_RX_FIFO_2_THRESHOLD 0x485c /* Rx FIFO 2 threshold */ #define RM9000_RX_FIFO_3_THRESHOLD 0x4868 /* Rx FIFO 3 threshold */ #define RM9000_RX_FIFO_4_THRESHOLD 0x4874 /* Rx FIFO 4 threshold */ #define RM9000_RX_FIFO_5_THRESHOLD 0x4880 /* Rx FIFO 5 threshold */ #define RM9000_RX_FIFO_6_THRESHOLD 0x488c /* Rx FIFO 6 threshold */ #define RM9000_RX_FIFO_7_THRESHOLD 0x4898 /* Rx FIFO 7 threshold */ #define RM9000_RX_FIFO_8_THRESHOLD 0x48a4 /* Rx FIFO 8 threshold */ #define RM9000_RX_FIFO_9_THRESHOLD 0x48b0 /* Rx FIFO 9 threshold */ #define RM9000_RX_FIFO_10_THRESHOLD 0x48bc /* Rx FIFO 10 threshold */ #define RM9000_RX_FIFO_11_THRESHOLD 0x48c8 /* Rx FIFO 11 threshold */ #define RM9000_TX_FIFO_0_THRESHOLD 0x4944 /* Tx FIFO 0 threshold */ #define RM9000_TX_FIFO_1_THRESHOLD 0x4950 /* Tx FIFO 1 threshold */ #define RM9000_TX_FIFO_2_THRESHOLD 0x495c /* Tx FIFO 2 threshold */ #define RM9000_RX_FIFO_0_COUNT 0x4848 /* Rx FIFO 0 count */ #define RM9000_RX_FIFO_1_COUNT 0x4854 /* Rx FIFO 1 count */ #define RM9000_RX_FIFO_2_COUNT 0x4860 /* Rx FIFO 2 count */ #define RM9000_RX_FIFO_3_COUNT 0x486c /* Rx FIFO 3 count */ #define RM9000_RX_FIFO_4_COUNT 0x4878 /* Rx FIFO 4 count */ #define RM9000_RX_FIFO_5_COUNT 0x4884 /* Rx FIFO 5 count */ #define RM9000_RX_FIFO_6_COUNT 0x4890 /* Rx FIFO 6 count */ #define RM9000_RX_FIFO_7_COUNT 0x489c /* Rx FIFO 7 count */ #define RM9000_RX_FIFO_8_COUNT 0x48a8 /* Rx FIFO 8 count */ #define RM9000_RX_FIFO_9_COUNT 0x48b4 /* Rx FIFO 9 count */ #define RM9000_RX_FIFO_10_COUNT 0x48c0 /* Rx FIFO 10 count */ #define RM9000_RX_FIFO_11_COUNT 0x48cc /* Rx FIFO 11 count */ #define RM9000_TX_FIFO_0_COUNT 0x4948 /* Tx FIFO 0 count */ #define RM9000_TX_FIFO_1_COUNT 0x4954 /* Tx FIFO 1 count */ #define RM9000_TX_FIFO_2_COUNT 0x4960 /* Tx FIFO 2 count */ /* AFX (Address Filter Exact) register offsets for Slice 0 */ #define RM9000_GE_AFX_EXACT_MATCH_LOW 0x1100 /* AFX Exact Match Address Low*/ #define RM9000_GE_AFX_EXACT_MATCH_MID 0x1104 /* AFX Exact Match Address Mid*/ #define RM9000_GE_AFX_EXACT_MATCH_HIGH 0x1108 /* AFX Exact Match Address Hi */ #define RM9000_GE_AFX_EXACT_MATCH_VID 0x110C /* AFX Exact Match VID */ #define RM9000_GE_AFX_MULTICAST_HASH_LOW 0x1110 /* AFX Multicast HASH Low */ #define RM9000_GE_AFX_MULTICAST_HASH_MIDLOW 0x1114 /* AFX Multicast HASH MidLow */ #define RM9000_GE_AFX_MULTICAST_HASH_MIDHI 0x1118 /* AFX Multicast HASH MidHi */ #define RM9000_GE_AFX_MULTICAST_HASH_HI 0x111C /* AFX Multicast HASH Hi */ #define RM9000_GE_AFX_ADDRS_FILTER_CTRL_0 0x1120 /* AFX Address Filter Ctrl 0 */ #define RM9000_GE_AFX_ADDRS_FILTER_CTRL_1 0x1124 /* AFX Address Filter Ctrl 1 */ #define RM9000_GE_AFX_ADDRS_FILTER_CTRL_2 0x1128 /* AFX Address Filter Ctrl 2 */ /* Traffic Groomer block */ #define RM9000_GE_TRTG_CONFIG_PORT_0 0x1000 /* TRTG port 0 config */ #define RM9000_GE_TRTG_CONFIG_PORT_1 0x2000 /* TRTG port 1 config */ #define RM9000_GE_TRTG_CONFIG_PORT_2 0x3000 /* TRTG port 2 config */ /* * Ethernet statistics */ #define RM9000_GE_MSTATX_CONTROL_PORT_0 0x0828 /* MSTATX control port 0 */ #define RM9000_GE_MSTATX_CONTROL_PORT_1 0x1828 /* MSTATX control port 1 */ #define RM9000_GE_MSTATX_CONTROL_PORT_2 0x2828 /* MSTATX control port 2 */ #define RM9000_GE_RX_FRAMES_OK_LOW_PORT_0 0x0840 /* RXFramesOK port 0, bits 15:0 */ #define RM9000_GE_RX_FRAMES_OK_LOW_PORT_1 0x1840 /* RXFramesOK port 1, bits 15:0 */ #define RM9000_GE_RX_FRAMES_OK_LOW_PORT_2 0x2840 /* RXFramesOK port 2, bits 15:0 */ #define RM9000_GE_RX_FRAMES_OK_MID_PORT_0 0x0844 /* RXFramesOK port 0, bits 31:16 */ #define RM9000_GE_RX_FRAMES_OK_MID_PORT_1 0x1844 /* RXFramesOK port 1, bits 31:16 */ #define RM9000_GE_RX_FRAMES_OK_MID_PORT_2 0x2844 /* RXFramesOK port 2, bits 31:16 */ #define RM9000_GE_RX_FRAMES_OK_HIGH_PORT_0 0x0848 /* RXFramesOK port 0, bits 39:32 */ #define RM9000_GE_RX_FRAMES_OK_HIGH_PORT_1 0x1848 /* RXFramesOK port 1, bits 39:32 */ #define RM9000_GE_RX_FRAMES_OK_HIGH_PORT_2 0x2848 /* RXFramesOK port 2, bits 39:32 */ #define RM9000_GE_RX_OCTETS_OK_LOW_PORT_0 0x0850 /* RXOctetsOK port 0, bits 15:0 */ #define RM9000_GE_RX_OCTETS_OK_LOW_PORT_1 0x1850 /* RXOctetsOK port 1, bits 15:0 */ #define RM9000_GE_RX_OCTETS_OK_LOW_PORT_2 0x2850 /* RXOctetsOK port 2, bits 15:0 */ #define RM9000_GE_RX_OCTETS_OK_MID_PORT_0 0x0854 /* RXOctetsOK port 0, bits 31:16 */ #define RM9000_GE_RX_OCTETS_OK_MID_PORT_1 0x1854 /* RXOctetsOK port 1, bits 31:16 */ #define RM9000_GE_RX_OCTETS_OK_MID_PORT_2 0x2854 /* RXOctetsOK port 2, bits 31:16 */ #define RM9000_GE_RX_OCTETS_OK_HIGH_PORT_0 0x0858 /* RXOctetsOK port 0, bits 39:32 */ #define RM9000_GE_RX_OCTETS_OK_HIGH_PORT_1 0x1858 /* RXOctetsOK port 1, bits 39:32 */ #define RM9000_GE_RX_OCTETS_OK_HIGH_PORT_2 0x2858 /* RXOctetsOK port 2, bits 39:32 */ #define RM9000_GE_RX_FRAMES_LOW_PORT_0 0x0860 /* RXFrames port 0, bits 15:0 */ #define RM9000_GE_RX_FRAMES_LOW_PORT_1 0x1860 /* RXFrames port 1, bits 15:0 */ #define RM9000_GE_RX_FRAMES_LOW_PORT_2 0x2860 /* RXFrames port 2, bits 15:0 */ #define RM9000_GE_RX_FRAMES_MID_PORT_0 0x0864 /* RXFrames port 0, bits 31:16 */ #define RM9000_GE_RX_FRAMES_MID_PORT_1 0x1864 /* RXFrames port 1, bits 31:16 */ #define RM9000_GE_RX_FRAMES_MID_PORT_2 0x2864 /* RXFrames port 2, bits 31:16 */ #define RM9000_GE_RX_FRAMES_HIGH_PORT_0 0x0868 /* RXFrames port 0, bits 39:32 */ #define RM9000_GE_RX_FRAMES_HIGH_PORT_1 0x1868 /* RXFrames port 1, bits 39:32 */ #define RM9000_GE_RX_FRAMES_HIGH_PORT_2 0x2868 /* RXFrames port 2, bits 39:32 */ #define RM9000_GE_RX_OCTETS_LOW_PORT_0 0x0870 /* RXOctets port 0, bits 15:0 */ #define RM9000_GE_RX_OCTETS_LOW_PORT_1 0x1870 /* RXOctets port 1, bits 15:0 */ #define RM9000_GE_RX_OCTETS_LOW_PORT_2 0x2870 /* RXOctets port 2, bits 15:0 */ #define RM9000_GE_RX_OCTETS_MID_PORT_0 0x0874 /* RXOctets port 0, bits 31:16 */ #define RM9000_GE_RX_OCTETS_MID_PORT_1 0x1874 /* RXOctets port 1, bits 31:16 */ #define RM9000_GE_RX_OCTETS_MID_PORT_2 0x2874 /* RXOctets port 2, bits 31:16 */ #define RM9000_GE_RX_OCTETS_HIGH_PORT_0 0x0878 /* RXOctets port 0, bits 39:32 */ #define RM9000_GE_RX_OCTETS_HIGH_PORT_1 0x1878 /* RXOctets port 1, bits 39:32 */ #define RM9000_GE_RX_OCTETS_HIGH_PORT_2 0x2878 /* RXOctets port 2, bits 39:32 */ #define RM9000_GE_RX_UNICAST_FRAMES_OK_LOW_PORT_0 0x0880 /* RXUnicastFramesOK port 0, bits 15:0 */ #define RM9000_GE_RX_UNICAST_FRAMES_OK_LOW_PORT_1 0x1880 /* RXUnicastFramesOK port 1, bits 15:0 */ #define RM9000_GE_RX_UNICAST_FRAMES_OK_LOW_PORT_2 0x2880 /* RXUnicastFramesOK port 2, bits 15:0 */ #define RM9000_GE_RX_UNICAST_FRAMES_OK_MID_PORT_0 0x0884 /* RXUnicastFramesOK port 0, bits 31:16 */ #define RM9000_GE_RX_UNICAST_FRAMES_OK_MID_PORT_1 0x1884 /* RXUnicastFramesOK port 1, bits 31:16 */ #define RM9000_GE_RX_UNICAST_FRAMES_OK_MID_PORT_2 0x2884 /* RXUnicastFramesOK port 2, bits 31:16 */ #define RM9000_GE_RX_UNICAST_FRAMES_OK_HIGH_PORT_0 0x0888 /* RXUnicastFramesOK port 0, bits 39:32 */ #define RM9000_GE_RX_UNICAST_FRAMES_OK_HIGH_PORT_1 0x1888 /* RXUnicastFramesOK port 1, bits 39:32 */ #define RM9000_GE_RX_UNICAST_FRAMES_OK_HIGH_PORT_2 0x2888 /* RXUnicastFramesOK port 2, bits 39:32 */ #define RM9000_GE_RX_BROADCAST_FRAMES_OK_LOW_PORT_0 0x0890 /* RXBroadcastFramesOK port 0, bits 15:0 */ #define RM9000_GE_RX_BROADCAST_FRAMES_OK_LOW_PORT_1 0x1890 /* RXBroadcastFramesOK port 1, bits 15:0 */ #define RM9000_GE_RX_BROADCAST_FRAMES_OK_LOW_PORT_2 0x2890 /* RXBroadcastFramesOK port 2, bits 15:0 */ #define RM9000_GE_RX_BROADCAST_FRAMES_OK_MID_PORT_0 0x0894 /* RXBroadcastFramesOK port 0, bits 31:16 */ #define RM9000_GE_RX_BROADCAST_FRAMES_OK_MID_PORT_1 0x1894 /* RXBroadcastFramesOK port 1, bits 31:16 */ #define RM9000_GE_RX_BROADCAST_FRAMES_OK_MID_PORT_2 0x2894 /* RXBroadcastFramesOK port 2, bits 31:16 */ #define RM9000_GE_RX_BROADCAST_FRAMES_OK_HIGH_PORT_0 0x0898 /* RXBroadcastFramesOK port 0, bits 39:32 */ #define RM9000_GE_RX_BROADCAST_FRAMES_OK_HIGH_PORT_1 0x1898 /* RXBroadcastFramesOK port 1, bits 39:32 */ #define RM9000_GE_RX_BROADCAST_FRAMES_OK_HIGH_PORT_2 0x2898 /* RXBroadcastFramesOK port 2, bits 39:32 */ #define RM9000_GE_RX_MULTICAST_FRAMES_OK_LOW_PORT_0 0x08a0 /* RXMulticastFramesOK port 0, bits 15:0 */ #define RM9000_GE_RX_MULTICAST_FRAMES_OK_LOW_PORT_1 0x18a0 /* RXMulticastFramesOK port 1, bits 15:0 */ #define RM9000_GE_RX_MULTICAST_FRAMES_OK_LOW_PORT_2 0x28a0 /* RXMulticastFramesOK port 2, bits 15:0 */ #define RM9000_GE_RX_MULTICAST_FRAMES_OK_MID_PORT_0 0x08a4 /* RXMulticastFramesOK port 0, bits 31:16 */ #define RM9000_GE_RX_MULTICAST_FRAMES_OK_MID_PORT_1 0x18a4 /* RXMulticastFramesOK port 1, bits 31:16 */ #define RM9000_GE_RX_MULTICAST_FRAMES_OK_MID_PORT_2 0x28a4 /* RXMulticastFramesOK port 2, bits 31:16 */ #define RM9000_GE_RX_MULTICAST_FRAMES_OK_HIGH_PORT_0 0x08a8 /* RXMulticastFramesOK port 0, bits 39:32 */ #define RM9000_GE_RX_MULTICAST_FRAMES_OK_HIGH_PORT_1 0x18a8 /* RXMulticastFramesOK port 1, bits 39:32 */ #define RM9000_GE_RX_MULTICAST_FRAMES_OK_HIGH_PORT_2 0x28a8 /* RXMulticastFramesOK port 2, bits 39:32 */ #define RM9000_GE_RX_TAGGED_FRAMES_OK_LOW_PORT_0 0x08b0 /* RXTaggedFramesOK port 0, bits 15:0 */ #define RM9000_GE_RX_TAGGED_FRAMES_OK_LOW_PORT_1 0x18b0 /* RXTaggedFramesOK port 1, bits 15:0 */ #define RM9000_GE_RX_TAGGED_FRAMES_OK_LOW_PORT_2 0x28b0 /* RXTaggedFramesOK port 2, bits 15:0 */ #define RM9000_GE_RX_TAGGED_FRAMES_OK_MID_PORT_0 0x08b4 /* RXTaggedFramesOK port 0, bits 31:16 */ #define RM9000_GE_RX_TAGGED_FRAMES_OK_MID_PORT_1 0x18b4 /* RXTaggedFramesOK port 1, bits 31:16 */ #define RM9000_GE_RX_TAGGED_FRAMES_OK_MID_PORT_2 0x28b4 /* RXTaggedFramesOK port 2, bits 31:16 */ #define RM9000_GE_RX_TAGGED_FRAMES_OK_HIGH_PORT_0 0x08b8 /* RXTaggedFramesOK port 0, bits 39:32 */ #define RM9000_GE_RX_TAGGED_FRAMES_OK_HIGH_PORT_1 0x18b8 /* RXTaggedFramesOK port 1, bits 39:32 */ #define RM9000_GE_RX_TAGGED_FRAMES_OK_HIGH_PORT_2 0x28b8 /* RXTaggedFramesOK port 2, bits 39:32 */ #define RM9000_GE_RX_PAUSE_FRAMES_OK_LOW_PORT_0 0x08c0 /* RXPauseFramesOK port 0, bits 15:0 */ #define RM9000_GE_RX_PAUSE_FRAMES_OK_LOW_PORT_1 0x18c0 /* RXPauseFramesOK port 1, bits 15:0 */ #define RM9000_GE_RX_PAUSE_FRAMES_OK_LOW_PORT_2 0x28c0 /* RXPauseFramesOK port 2, bits 15:0 */ #define RM9000_GE_RX_PAUSE_FRAMES_OK_MID_PORT_0 0x08c4 /* RXPauseFramesOK port 0, bits 31:16 */ #define RM9000_GE_RX_PAUSE_FRAMES_OK_MID_PORT_1 0x18c4 /* RXPauseFramesOK port 1, bits 31:16 */ #define RM9000_GE_RX_PAUSE_FRAMES_OK_MID_PORT_2 0x28c4 /* RXPauseFramesOK port 2, bits 31:16 */ #define RM9000_GE_RX_PAUSE_FRAMES_OK_HIGH_PORT_0 0x08c8 /* RXPauseFramesOK port 0, bits 39:32 */ #define RM9000_GE_RX_PAUSE_FRAMES_OK_HIGH_PORT_1 0x18c8 /* RXPauseFramesOK port 1, bits 39:32 */ #define RM9000_GE_RX_PAUSE_FRAMES_OK_HIGH_PORT_2 0x28c8 /* RXPauseFramesOK port 2, bits 39:32 */ #define RM9000_GE_RX_MAC_CONTROL_FRAMES_OK_LOW_PORT_0 0x08d0 /* RXMacControlFramesOK port 0, bits 15:0 */ #define RM9000_GE_RX_MAC_CONTROL_FRAMES_OK_LOW_PORT_1 0x18d0 /* RXMacControlFramesOK port 1, bits 15:0 */ #define RM9000_GE_RX_MAC_CONTROL_FRAMES_OK_LOW_PORT_2 0x28d0 /* RXMacControlFramesOK port 2, bits 15:0 */ #define RM9000_GE_RX_MAC_CONTROL_FRAMES_OK_MID_PORT_0 0x08d4 /* RXMacControlFramesOK port 0, bits 31:16 */ #define RM9000_GE_RX_MAC_CONTROL_FRAMES_OK_MID_PORT_1 0x18d4 /* RXMacControlFramesOK port 1, bits 31:16 */ #define RM9000_GE_RX_MAC_CONTROL_FRAMES_OK_MID_PORT_2 0x28d4 /* RXMacControlFramesOK port 2, bits 31:16 */ #define RM9000_GE_RX_MAC_CONTROL_FRAMES_OK_HIGH_PORT_0 0x08d8 /* RXMacControlFramesOK port 0, bits 39:32 */ #define RM9000_GE_RX_MAC_CONTROL_FRAMES_OK_HIGH_PORT_1 0x18d8 /* RXMacControlFramesOK port 1, bits 39:32 */ #define RM9000_GE_RX_MAC_CONTROL_FRAMES_OK_HIGH_PORT_2 0x28d8 /* RXMacControlFramesOK port 2, bits 39:32 */ #define RM9000_GE_RX_FCS_ERRORS_LOW_PORT_0 0x08e0 /* RXFCSErrors port 0, bits 15:0 */ #define RM9000_GE_RX_FCS_ERRORS_LOW_PORT_1 0x18e0 /* RXFCSErrors port 1, bits 15:0 */ #define RM9000_GE_RX_FCS_ERRORS_LOW_PORT_2 0x28e0 /* RXFCSErrors port 2, bits 15:0 */ #define RM9000_GE_RX_FCS_ERRORS_MID_PORT_0 0x08e4 /* RXFCSErrors port 0, bits 31:16 */ #define RM9000_GE_RX_FCS_ERRORS_MID_PORT_1 0x18e4 /* RXFCSErrors port 1, bits 31:16 */ #define RM9000_GE_RX_FCS_ERRORS_MID_PORT_2 0x28e4 /* RXFCSErrors port 2, bits 31:16 */ #define RM9000_GE_RX_FCS_ERRORS_HIGH_PORT_0 0x08e8 /* RXFCSErrors port 0, bits 39:32 */ #define RM9000_GE_RX_FCS_ERRORS_HIGH_PORT_1 0x18e8 /* RXFCSErrors port 1, bits 39:32 */ #define RM9000_GE_RX_FCS_ERRORS_HIGH_PORT_2 0x28e8 /* RXFCSErrors port 2, bits 39:32 */ #define RM9000_GE_RX_ALIGNMENT_ERRORS_LOW_PORT_0 0x08f0 /* RXAlignmentErrors port 0, bits 15:0 */ #define RM9000_GE_RX_ALIGNMENT_ERRORS_LOW_PORT_1 0x18f0 /* RXAlignmentErrors port 1, bits 15:0 */ #define RM9000_GE_RX_ALIGNMENT_ERRORS_LOW_PORT_2 0x28f0 /* RXAlignmentErrors port 2, bits 15:0 */ #define RM9000_GE_RX_ALIGNMENT_ERRORS_MID_PORT_0 0x08f4 /* RXAlignmentErrors port 0, bits 31:16 */ #define RM9000_GE_RX_ALIGNMENT_ERRORS_MID_PORT_1 0x18f4 /* RXAlignmentErrors port 1, bits 31:16 */ #define RM9000_GE_RX_ALIGNMENT_ERRORS_MID_PORT_2 0x28f4 /* RXAlignmentErrors port 2, bits 31:16 */ #define RM9000_GE_RX_ALIGNMENT_ERRORS_HIGH_PORT_0 0x08f8 /* RXAlignmentErrors port 0, bits 39:32 */ #define RM9000_GE_RX_ALIGNMENT_ERRORS_HIGH_PORT_1 0x18f8 /* RXAlignmentErrors port 1, bits 39:32 */ #define RM9000_GE_RX_ALIGNMENT_ERRORS_HIGH_PORT_2 0x28f8 /* RXAlignmentErrors port 2, bits 39:32 */ #define RM9000_GE_RX_SYMBOL_ERRORS_LOW_PORT_0 0x0900 /* RXSymbolErrors port 0, bits 15:0 */ #define RM9000_GE_RX_SYMBOL_ERRORS_LOW_PORT_1 0x1900 /* RXSymbolErrors port 1, bits 15:0 */ #define RM9000_GE_RX_SYMBOL_ERRORS_LOW_PORT_2 0x2900 /* RXSymbolErrors port 2, bits 15:0 */ #define RM9000_GE_RX_SYMBOL_ERRORS_MID_PORT_0 0x0904 /* RXSymbolErrors port 0, bits 31:16 */ #define RM9000_GE_RX_SYMBOL_ERRORS_MID_PORT_1 0x1904 /* RXSymbolErrors port 1, bits 31:16 */ #define RM9000_GE_RX_SYMBOL_ERRORS_MID_PORT_2 0x2904 /* RXSymbolErrors port 2, bits 31:16 */ #define RM9000_GE_RX_SYMBOL_ERRORS_HIGH_PORT_0 0x0908 /* RXSymbolErrors port 0, bits 39:32 */ #define RM9000_GE_RX_SYMBOL_ERRORS_HIGH_PORT_1 0x1908 /* RXSymbolErrors port 1, bits 39:32 */ #define RM9000_GE_RX_SYMBOL_ERRORS_HIGH_PORT_2 0x2908 /* RXSymbolErrors port 2, bits 39:32 */ #define RM9000_GE_RX_LAYER1_ERRORS_LOW_PORT_0 0x0910 /* RXLayer1Errors port 0, bits 15:0 */ #define RM9000_GE_RX_LAYER1_ERRORS_LOW_PORT_1 0x1910 /* RXLayer1Errors port 1, bits 15:0 */ #define RM9000_GE_RX_LAYER1_ERRORS_LOW_PORT_2 0x2910 /* RXLayer1Errors port 2, bits 15:0 */ #define RM9000_GE_RX_LAYER1_ERRORS_MID_PORT_0 0x0914 /* RXLayer1Errors port 0, bits 31:16 */ #define RM9000_GE_RX_LAYER1_ERRORS_MID_PORT_1 0x1914 /* RXLayer1Errors port 1, bits 31:16 */ #define RM9000_GE_RX_LAYER1_ERRORS_MID_PORT_2 0x2914 /* RXLayer1Errors port 2, bits 31:16 */ #define RM9000_GE_RX_LAYER1_ERRORS_HIGH_PORT_0 0x0918 /* RXLayer1Errors port 0, bits 39:32 */ #define RM9000_GE_RX_LAYER1_ERRORS_HIGH_PORT_1 0x1918 /* RXLayer1Errors port 1, bits 39:32 */ #define RM9000_GE_RX_LAYER1_ERRORS_HIGH_PORT_2 0x2918 /* RXLayer1Errors port 2, bits 39:32 */ #define RM9000_GE_RX_INRANGELENGTH_ERRORS_LOW_PORT_0 0x0920 /* RXInRangeLengthErrors port 0, bits 15:0 */ #define RM9000_GE_RX_INRANGELENGTH_ERRORS_LOW_PORT_1 0x1920 /* RXInRangeLengthErrors port 1, bits 15:0 */ #define RM9000_GE_RX_INRANGELENGTH_ERRORS_LOW_PORT_2 0x2920 /* RXInRangeLengthErrors port 2, bits 15:0 */ #define RM9000_GE_RX_INRANGELENGTH_ERRORS_MID_PORT_0 0x0924 /* RXInRangeLengthErrors port 0, bits 31:16 */ #define RM9000_GE_RX_INRANGELENGTH_ERRORS_MID_PORT_1 0x1924 /* RXInRangeLengthErrors port 1, bits 31:16 */ #define RM9000_GE_RX_INRANGELENGTH_ERRORS_MID_PORT_2 0x2924 /* RXInRangeLengthErrors port 2, bits 31:16 */ #define RM9000_GE_RX_INRANGELENGTH_ERRORS_HIGH_PORT_0 0x0928 /* RXInRangeLengthErrors port 0, bits 39:32 */ #define RM9000_GE_RX_INRANGELENGTH_ERRORS_HIGH_PORT_1 0x1928 /* RXInRangeLengthErrors port 1, bits 39:32 */ #define RM9000_GE_RX_INRANGELENGTH_ERRORS_HIGH_PORT_2 0x2928 /* RXInRangeLengthErrors port 2, bits 39:32 */ #define RM9000_GE_RX_LONGLENGTH_ERRORS_LOW_PORT_0 0x0930 /* RXLongLengthErrors port 0, bits 15:0 */ #define RM9000_GE_RX_LONGLENGTH_ERRORS_LOW_PORT_1 0x1930 /* RXLongLengthErrors port 1, bits 15:0 */ #define RM9000_GE_RX_LONGLENGTH_ERRORS_LOW_PORT_2 0x2930 /* RXLongLengthErrors port 2, bits 15:0 */ #define RM9000_GE_RX_LONGLENGTH_ERRORS_MID_PORT_0 0x0934 /* RXLongLengthErrors port 0, bits 31:16 */ #define RM9000_GE_RX_LONGLENGTH_ERRORS_MID_PORT_1 0x1934 /* RXLongLengthErrors port 1, bits 31:16 */ #define RM9000_GE_RX_LONGLENGTH_ERRORS_MID_PORT_2 0x2934 /* RXLongLengthErrors port 2, bits 31:16 */ #define RM9000_GE_RX_LONGLENGTH_ERRORS_HIGH_PORT_0 0x0938 /* RXLongLengthErrors port 0, bits 39:32 */ #define RM9000_GE_RX_LONGLENGTH_ERRORS_HIGH_PORT_1 0x1938 /* RXLongLengthErrors port 1, bits 39:32 */ #define RM9000_GE_RX_LONGLENGTH_ERRORS_HIGH_PORT_2 0x2938 /* RXLongLengthErrors port 2, bits 39:32 */ #define RM9000_GE_RX_LONGLENGTHCRC_ERRORS_LOW_PORT_0 0x0940 /* RXLongLengthCRCErrors port 0, bits 15:0 */ #define RM9000_GE_RX_LONGLENGTHCRC_ERRORS_LOW_PORT_1 0x1940 /* RXLongLengthCRCErrors port 1, bits 15:0 */ #define RM9000_GE_RX_LONGLENGTHCRC_ERRORS_LOW_PORT_2 0x2940 /* RXLongLengthCRCErrors port 2, bits 15:0 */ #define RM9000_GE_RX_LONGLENGTHCRC_ERRORS_MID_PORT_0 0x0944 /* RXLongLengthCRCErrors port 0, bits 31:16 */ #define RM9000_GE_RX_LONGLENGTHCRC_ERRORS_MID_PORT_1 0x1944 /* RXLongLengthCRCErrors port 1, bits 31:16 */ #define RM9000_GE_RX_LONGLENGTHCRC_ERRORS_MID_PORT_2 0x2944 /* RXLongLengthCRCErrors port 2, bits 31:16 */ #define RM9000_GE_RX_LONGLENGTHCRC_ERRORS_HIGH_PORT_0 0x0948 /* RXLongLengthCRCErrors port 0, bits 39:32 */ #define RM9000_GE_RX_LONGLENGTHCRC_ERRORS_HIGH_PORT_1 0x1948 /* RXLongLengthCRCErrors port 1, bits 39:32 */ #define RM9000_GE_RX_LONGLENGTHCRC_ERRORS_HIGH_PORT_2 0x2948 /* RXLongLengthCRCErrors port 2, bits 39:32 */ #define RM9000_GE_RX_SHORTLENGTH_ERRORS_LOW_PORT_0 0x0950 /* RXShortLengthErrors port 0, bits 15:0 */ #define RM9000_GE_RX_SHORTLENGTH_ERRORS_LOW_PORT_1 0x1950 /* RXShortLengthErrors port 1, bits 15:0 */ #define RM9000_GE_RX_SHORTLENGTH_ERRORS_LOW_PORT_2 0x2950 /* RXShortLengthErrors port 2, bits 15:0 */ #define RM9000_GE_RX_SHORTLENGTH_ERRORS_MID_PORT_0 0x0954 /* RXShortLengthErrors port 0, bits 31:16 */ #define RM9000_GE_RX_SHORTLENGTH_ERRORS_MID_PORT_1 0x1954 /* RXShortLengthErrors port 1, bits 31:16 */ #define RM9000_GE_RX_SHORTLENGTH_ERRORS_MID_PORT_2 0x2954 /* RXShortLengthErrors port 2, bits 31:16 */ #define RM9000_GE_RX_SHORTLENGTH_ERRORS_HIGH_PORT_0 0x0958 /* RXShortLengthErrors port 0, bits 39:32 */ #define RM9000_GE_RX_SHORTLENGTH_ERRORS_HIGH_PORT_1 0x1958 /* RXShortLengthErrors port 1, bits 39:32 */ #define RM9000_GE_RX_SHORTLENGTH_ERRORS_HIGH_PORT_2 0x2958 /* RXShortLengthErrors port 2, bits 39:32 */ #define RM9000_GE_RX_SHORTLENGTHCRC_ERRORS_LOW_PORT_0 0x0960 /* RXShortLengthCRCErrors port 0, bits 15:0 */ #define RM9000_GE_RX_SHORTLENGTHCRC_ERRORS_LOW_PORT_1 0x1960 /* RXShortLengthCRCErrors port 1, bits 15:0 */ #define RM9000_GE_RX_SHORTLENGTHCRC_ERRORS_LOW_PORT_2 0x2960 /* RXShortLengthCRCErrors port 2, bits 15:0 */ #define RM9000_GE_RX_SHORTLENGTHCRC_ERRORS_MID_PORT_0 0x0964 /* RXShortLengthCRCErrors port 0, bits 31:16 */ #define RM9000_GE_RX_SHORTLENGTHCRC_ERRORS_MID_PORT_1 0x1964 /* RXShortLengthCRCErrors port 1, bits 31:16 */ #define RM9000_GE_RX_SHORTLENGTHCRC_ERRORS_MID_PORT_2 0x2964 /* RXShortLengthCRCErrors port 2, bits 31:16 */ #define RM9000_GE_RX_SHORTLENGTHCRC_ERRORS_HIGH_PORT_0 0x0968 /* RXShortLengthCRCErrors port 0, bits 39:32 */ #define RM9000_GE_RX_SHORTLENGTHCRC_ERRORS_HIGH_PORT_1 0x1968 /* RXShortLengthCRCErrors port 1, bits 39:32 */ #define RM9000_GE_RX_SHORTLENGTHCRC_ERRORS_HIGH_PORT_2 0x2968 /* RXShortLengthCRCErrors port 2, bits 39:32 */ #define RM9000_GE_RX_FRAMES64OCTETS_LOW_PORT_0 0x0970 /* RXFrames64Octets port 0, bits 15:0 */ #define RM9000_GE_RX_FRAMES64OCTETS_LOW_PORT_1 0x1970 /* RXFrames64Octets port 1, bits 15:0 */ #define RM9000_GE_RX_FRAMES64OCTETS_LOW_PORT_2 0x2970 /* RXFrames64Octets port 2, bits 15:0 */ #define RM9000_GE_RX_FRAMES64OCTETS_MID_PORT_0 0x0974 /* RXFrames64Octets port 0, bits 31:16 */ #define RM9000_GE_RX_FRAMES64OCTETS_MID_PORT_1 0x1974 /* RXFrames64Octets port 1, bits 31:16 */ #define RM9000_GE_RX_FRAMES64OCTETS_MID_PORT_2 0x2974 /* RXFrames64Octets port 2, bits 31:16 */ #define RM9000_GE_RX_FRAMES64OCTETS_HIGH_PORT_0 0x0978 /* RXFrames64Octets port 0, bits 39:32 */ #define RM9000_GE_RX_FRAMES64OCTETS_HIGH_PORT_1 0x1978 /* RXFrames64Octets port 1, bits 39:32 */ #define RM9000_GE_RX_FRAMES64OCTETS_HIGH_PORT_2 0x2978 /* RXFrames64Octets port 2, bits 39:32 */ #define RM9000_GE_RX_FRAMES65TO127OCTETS_LOW_PORT_0 0x0980 /* RXFrames65to127Octets port 0, bits 15:0 */ #define RM9000_GE_RX_FRAMES65TO127OCTETS_LOW_PORT_1 0x1980 /* RXFrames65to127Octets port 1, bits 15:0 */ #define RM9000_GE_RX_FRAMES65TO127OCTETS_LOW_PORT_2 0x2980 /* RXFrames65to127Octets port 2, bits 15:0 */ #define RM9000_GE_RX_FRAMES65TO127OCTETS_MID_PORT_0 0x0984 /* RXFrames65to127Octets port 0, bits 31:16 */ #define RM9000_GE_RX_FRAMES65TO127OCTETS_MID_PORT_1 0x1984 /* RXFrames65to127Octets port 1, bits 31:16 */ #define RM9000_GE_RX_FRAMES65TO127OCTETS_MID_PORT_2 0x2984 /* RXFrames65to127Octets port 2, bits 31:16 */ #define RM9000_GE_RX_FRAMES65TO127OCTETS_HIGH_PORT_0 0x0988 /* RXFrames65to127Octets port 0, bits 39:32 */ #define RM9000_GE_RX_FRAMES65TO127OCTETS_HIGH_PORT_1 0x1988 /* RXFrames65to127Octets port 1, bits 39:32 */ #define RM9000_GE_RX_FRAMES65TO127OCTETS_HIGH_PORT_2 0x2988 /* RXFrames65to127Octets port 2, bits 39:32 */ #define RM9000_GE_RX_FRAMES128TO255OCTETS_LOW_PORT_0 0x0990 /* RXFrames128to255Octets port 0, bits 15:0 */ #define RM9000_GE_RX_FRAMES128TO255OCTETS_LOW_PORT_1 0x1990 /* RXFrames128to255Octets port 1, bits 15:0 */ #define RM9000_GE_RX_FRAMES128TO255OCTETS_LOW_PORT_2 0x2990 /* RXFrames128to255Octets port 2, bits 15:0 */ #define RM9000_GE_RX_FRAMES128TO255OCTETS_MID_PORT_0 0x0994 /* RXFrames128to255Octets port 0, bits 31:16 */ #define RM9000_GE_RX_FRAMES128TO255OCTETS_MID_PORT_1 0x1994 /* RXFrames128to255Octets port 1, bits 31:16 */ #define RM9000_GE_RX_FRAMES128TO255OCTETS_MID_PORT_2 0x2994 /* RXFrames128to255Octets port 2, bits 31:16 */ #define RM9000_GE_RX_FRAMES128TO255OCTETS_HIGH_PORT_0 0x0998 /* RXFrames128to255Octets port 0, bits 39:32 */ #define RM9000_GE_RX_FRAMES128TO255OCTETS_HIGH_PORT_1 0x1998 /* RXFrames128to255Octets port 1, bits 39:32 */ #define RM9000_GE_RX_FRAMES128TO255OCTETS_HIGH_PORT_2 0x2998 /* RXFrames128to255Octets port 2, bits 39:32 */ #define RM9000_GE_RX_FRAMES256TO511OCTETS_LOW_PORT_0 0x09a0 /* RXFrames256to511Octets port 0, bits 15:0 */ #define RM9000_GE_RX_FRAMES256TO511OCTETS_LOW_PORT_1 0x19a0 /* RXFrames256to511Octets port 1, bits 15:0 */ #define RM9000_GE_RX_FRAMES256TO511OCTETS_LOW_PORT_2 0x29a0 /* RXFrames256to511Octets port 2, bits 15:0 */ #define RM9000_GE_RX_FRAMES256TO511OCTETS_MID_PORT_0 0x09a4 /* RXFrames256to511Octets port 0, bits 31:16 */ #define RM9000_GE_RX_FRAMES256TO511OCTETS_MID_PORT_1 0x19a4 /* RXFrames256to511Octets port 1, bits 31:16 */ #define RM9000_GE_RX_FRAMES256TO511OCTETS_MID_PORT_2 0x29a4 /* RXFrames256to511Octets port 2, bits 31:16 */ #define RM9000_GE_RX_FRAMES256TO511OCTETS_HIGH_PORT_0 0x09a8 /* RXFrames256to511Octets port 0, bits 39:32 */ #define RM9000_GE_RX_FRAMES256TO511OCTETS_HIGH_PORT_1 0x19a8 /* RXFrames256to511Octets port 1, bits 39:32 */ #define RM9000_GE_RX_FRAMES256TO511OCTETS_HIGH_PORT_2 0x29a8 /* RXFrames256to511Octets port 2, bits 39:32 */ #define RM9000_GE_RX_FRAMES512TO1023OCTETS_LOW_PORT_0 0x09b0 /* RXFrames512to1023Octets port 0, bits 15:0 */ #define RM9000_GE_RX_FRAMES512TO1023OCTETS_LOW_PORT_1 0x19b0 /* RXFrames512to1023Octets port 1, bits 15:0 */ #define RM9000_GE_RX_FRAMES512TO1023OCTETS_LOW_PORT_2 0x29b0 /* RXFrames512to1023Octets port 2, bits 15:0 */ #define RM9000_GE_RX_FRAMES512TO1023OCTETS_MID_PORT_0 0x09b4 /* RXFrames512to1023Octets port 0, bits 31:16 */ #define RM9000_GE_RX_FRAMES512TO1023OCTETS_MID_PORT_1 0x19b4 /* RXFrames512to1023Octets port 1, bits 31:16 */ #define RM9000_GE_RX_FRAMES512TO1023OCTETS_MID_PORT_2 0x29b4 /* RXFrames512to1023Octets port 2, bits 31:16 */ #define RM9000_GE_RX_FRAMES512TO1023OCTETS_HIGH_PORT_0 0x09b8 /* RXFrames512to1023Octets port 0, bits 39:32 */ #define RM9000_GE_RX_FRAMES512TO1023OCTETS_HIGH_PORT_1 0x19b8 /* RXFrames512to1023Octets port 1, bits 39:32 */ #define RM9000_GE_RX_FRAMES512TO1023OCTETS_HIGH_PORT_2 0x29b8 /* RXFrames512to1023Octets port 2, bits 39:32 */ #define RM9000_GE_RX_FRAMES1024TO1518OCTETS_LOW_PORT_0 0x09c0 /* RXFrames1024to1518Octets port 0, bits 15:0 */ #define RM9000_GE_RX_FRAMES1024TO1518OCTETS_LOW_PORT_1 0x19c0 /* RXFrames1024to1518Octets port 1, bits 15:0 */ #define RM9000_GE_RX_FRAMES1024TO1518OCTETS_LOW_PORT_2 0x29c0 /* RXFrames1024to1518Octets port 2, bits 15:0 */ #define RM9000_GE_RX_FRAMES1024TO1518OCTETS_MID_PORT_0 0x09c4 /* RXFrames1024to1518Octets port 0, bits 31:16 */ #define RM9000_GE_RX_FRAMES1024TO1518OCTETS_MID_PORT_1 0x19c4 /* RXFrames1024to1518Octets port 1, bits 31:16 */ #define RM9000_GE_RX_FRAMES1024TO1518OCTETS_MID_PORT_2 0x29c4 /* RXFrames1024to1518Octets port 2, bits 31:16 */ #define RM9000_GE_RX_FRAMES1024TO1518OCTETS_HIGH_PORT_0 0x09c8 /* RXFrames1024to1518Octets port 0, bits 39:32 */ #define RM9000_GE_RX_FRAMES1024TO1518OCTETS_HIGH_PORT_1 0x19c8 /* RXFrames1024to1518Octets port 1, bits 39:32 */ #define RM9000_GE_RX_FRAMES1024TO1518OCTETS_HIGH_PORT_2 0x29c8 /* RXFrames1024to1518Octets port 2, bits 39:32 */ #define RM9000_GE_RX_FRAMES1519TOMAXOCTETS_LOW_PORT_0 0x09d0 /* RXFrames1519toMAXOctets port 0, bits 15:0 */ #define RM9000_GE_RX_FRAMES1519TOMAXOCTETS_LOW_PORT_1 0x19d0 /* RXFrames1519toMAXOctets port 1, bits 15:0 */ #define RM9000_GE_RX_FRAMES1519TOMAXOCTETS_LOW_PORT_2 0x29d0 /* RXFrames1519toMAXOctets port 2, bits 15:0 */ #define RM9000_GE_RX_FRAMES1519TOMAXOCTETS_MID_PORT_0 0x09d4 /* RXFrames1519toMAXOctets port 0, bits 31:16 */ #define RM9000_GE_RX_FRAMES1519TOMAXOCTETS_MID_PORT_1 0x19d4 /* RXFrames1519toMAXOctets port 1, bits 31:16 */ #define RM9000_GE_RX_FRAMES1519TOMAXOCTETS_MID_PORT_2 0x29d4 /* RXFrames1519toMAXOctets port 2, bits 31:16 */ #define RM9000_GE_RX_FRAMES1519TOMAXOCTETS_HIGH_PORT_0 0x09d8 /* RXFrames1519toMAXOctets port 0, bits 39:32 */ #define RM9000_GE_RX_FRAMES1519TOMAXOCTETS_HIGH_PORT_1 0x19d8 /* RXFrames1519toMAXOctets port 1, bits 39:32 */ #define RM9000_GE_RX_FRAMES1519TOMAXOCTETS_HIGH_PORT_2 0x29d8 /* RXFrames1519toMAXOctets port 2, bits 39:32 */ #define RM9000_GE_RX_STATIONADDRESSFILTERED_LOW_PORT_0 0x09e0 /* RXStationAddressFiltered port 0, bits 15:0 */ #define RM9000_GE_RX_STATIONADDRESSFILTERED_LOW_PORT_1 0x19e0 /* RXStationAddressFiltered port 1, bits 15:0 */ #define RM9000_GE_RX_STATIONADDRESSFILTERED_LOW_PORT_2 0x29e0 /* RXStationAddressFiltered port 2, bits 15:0 */ #define RM9000_GE_RX_STATIONADDRESSFILTERED_MID_PORT_0 0x09e4 /* RXStationAddressFiltered port 0, bits 31:16 */ #define RM9000_GE_RX_STATIONADDRESSFILTERED_MID_PORT_1 0x19e4 /* RXStationAddressFiltered port 1, bits 31:16 */ #define RM9000_GE_RX_STATIONADDRESSFILTERED_MID_PORT_2 0x29e4 /* RXStationAddressFiltered port 2, bits 31:16 */ #define RM9000_GE_RX_STATIONADDRESSFILTERED_HIGH_PORT_0 0x09e8 /* RXStationAddressFiltered port 0, bits 39:32 */ #define RM9000_GE_RX_STATIONADDRESSFILTERED_HIGH_PORT_1 0x19e8 /* RXStationAddressFiltered port 1, bits 39:32 */ #define RM9000_GE_RX_STATIONADDRESSFILTERED_HIGH_PORT_2 0x29e8 /* RXStationAddressFiltered port 2, bits 39:32 */ #define RM9000_GE_TX_FRAMES_OK_LOW_PORT_0 0x0a50 /* TXFramesOK port 0, bits 15:0 */ #define RM9000_GE_TX_FRAMES_OK_LOW_PORT_1 0x1a50 /* TXFramesOK port 1, bits 15:0 */ #define RM9000_GE_TX_FRAMES_OK_LOW_PORT_2 0x2a50 /* TXFramesOK port 2, bits 15:0 */ #define RM9000_GE_TX_FRAMES_OK_MID_PORT_0 0x0a54 /* TXFramesOK port 0, bits 31:16 */ #define RM9000_GE_TX_FRAMES_OK_MID_PORT_1 0x1a54 /* TXFramesOK port 1, bits 31:16 */ #define RM9000_GE_TX_FRAMES_OK_MID_PORT_2 0x2a54 /* TXFramesOK port 2, bits 31:16 */ #define RM9000_GE_TX_FRAMES_OK_HIGH_PORT_0 0x0a58 /* TXFramesOK port 0, bits 39:32 */ #define RM9000_GE_TX_FRAMES_OK_HIGH_PORT_1 0x1a58 /* TXFramesOK port 1, bits 39:32 */ #define RM9000_GE_TX_FRAMES_OK_HIGH_PORT_2 0x2a58 /* TXFramesOK port 2, bits 39:32 */ #define RM9000_GE_TX_OCTETS_OK_LOW_PORT_0 0x0a60 /* TXOctetsOK port 0, bits 15:0 */ #define RM9000_GE_TX_OCTETS_OK_LOW_PORT_1 0x1a60 /* TXOctetsOK port 1, bits 15:0 */ #define RM9000_GE_TX_OCTETS_OK_LOW_PORT_2 0x2a60 /* TXOctetsOK port 2, bits 15:0 */ #define RM9000_GE_TX_OCTETS_OK_MID_PORT_0 0x0a64 /* TXOctetsOK port 0, bits 31:16 */ #define RM9000_GE_TX_OCTETS_OK_MID_PORT_1 0x1a64 /* TXOctetsOK port 1, bits 31:16 */ #define RM9000_GE_TX_OCTETS_OK_MID_PORT_2 0x2a64 /* TXOctetsOK port 2, bits 31:16 */ #define RM9000_GE_TX_OCTETS_OK_HIGH_PORT_0 0x0a68 /* TXOctetsOK port 0, bits 39:32 */ #define RM9000_GE_TX_OCTETS_OK_HIGH_PORT_1 0x1a68 /* TXOctetsOK port 1, bits 39:32 */ #define RM9000_GE_TX_OCTETS_OK_HIGH_PORT_2 0x2a68 /* TXOctetsOK port 1, bits 39:32 */ #define RM9000_GE_TX_OCTETS_LOW_PORT_0 0x0a70 /* TXOctets port 0, bits 15:0 */ #define RM9000_GE_TX_OCTETS_LOW_PORT_1 0x1a70 /* TXOctets port 1, bits 15:0 */ #define RM9000_GE_TX_OCTETS_LOW_PORT_2 0x2a70 /* TXOctets port 2, bits 15:0 */ #define RM9000_GE_TX_OCTETS_MID_PORT_0 0x0a74 /* TXOctets port 0, bits 31:16 */ #define RM9000_GE_TX_OCTETS_MID_PORT_1 0x1a74 /* TXOctets port 1, bits 31:16 */ #define RM9000_GE_TX_OCTETS_MID_PORT_2 0x2a74 /* TXOctets port 2, bits 31:16 */ #define RM9000_GE_TX_OCTETS_HIGH_PORT_0 0x0a78 /* TXOctets port 0, bits 39:32 */ #define RM9000_GE_TX_OCTETS_HIGH_PORT_1 0x1a78 /* TXOctets port 1, bits 39:32 */ #define RM9000_GE_TX_OCTETS_HIGH_PORT_2 0x2a78 /* TXOctets port 2, bits 39:32 */ #define RM9000_GE_TX_TAGGED_FRAMES_OK_LOW_PORT_0 0x0a80 /* TXTaggedFramesOK port 0, bits 15:0 */ #define RM9000_GE_TX_TAGGED_FRAMES_OK_LOW_PORT_1 0x1a80 /* TXTaggedFramesOK port 1, bits 15:0 */ #define RM9000_GE_TX_TAGGED_FRAMES_OK_LOW_PORT_2 0x2a80 /* TXTaggedFramesOK port 2, bits 15:0 */ #define RM9000_GE_TX_TAGGED_FRAMES_OK_MID_PORT_0 0x0a84 /* TXTaggedFramesOK port 0, bits 31:16 */ #define RM9000_GE_TX_TAGGED_FRAMES_OK_MID_PORT_1 0x1a84 /* TXTaggedFramesOK port 1, bits 31:16 */ #define RM9000_GE_TX_TAGGED_FRAMES_OK_MID_PORT_2 0x2a84 /* TXTaggedFramesOK port 2, bits 31:16 */ #define RM9000_GE_TX_TAGGED_FRAMES_OK_HIGH_PORT_0 0x0a88 /* TXTaggedFramesOK port 0, bits 39:32 */ #define RM9000_GE_TX_TAGGED_FRAMES_OK_HIGH_PORT_1 0x1a88 /* TXTaggedFramesOK port 1, bits 39:32 */ #define RM9000_GE_TX_TAGGED_FRAMES_OK_HIGH_PORT_2 0x2a88 /* TXTaggedFramesOK port 2, bits 39:32 */ #define RM9000_GE_TX_PAUSE_FRAMES_OK_LOW_PORT_0 0x0a90 /* TXPauseFramesOK port 0, bits 15:0 */ #define RM9000_GE_TX_PAUSE_FRAMES_OK_LOW_PORT_1 0x1a90 /* TXPauseFramesOK port 1, bits 15:0 */ #define RM9000_GE_TX_PAUSE_FRAMES_OK_LOW_PORT_2 0x2a90 /* TXPauseFramesOK port 2, bits 15:0 */ #define RM9000_GE_TX_PAUSE_FRAMES_OK_MID_PORT_0 0x0a94 /* TXPauseFramesOK port 0, bits 31:16 */ #define RM9000_GE_TX_PAUSE_FRAMES_OK_MID_PORT_1 0x1a94 /* TXPauseFramesOK port 1, bits 31:16 */ #define RM9000_GE_TX_PAUSE_FRAMES_OK_MID_PORT_2 0x2a94 /* TXPauseFramesOK port 2, bits 31:16 */ #define RM9000_GE_TX_PAUSE_FRAMES_OK_HIGH_PORT_0 0x0a98 /* TXPauseFramesOK port 0, bits 39:32 */ #define RM9000_GE_TX_PAUSE_FRAMES_OK_HIGH_PORT_1 0x1a98 /* TXPauseFramesOK port 1, bits 39:32 */ #define RM9000_GE_TX_PAUSE_FRAMES_OK_HIGH_PORT_2 0x2a98 /* TXPauseFramesOK port 2, bits 39:32 */ #define RM9000_GE_TX_FCS_ERRORS_LOW_PORT_0 0x08a0 /* TXFCSErrors port 0, bits 15:0 */ #define RM9000_GE_TX_FCS_ERRORS_LOW_PORT_1 0x18a0 /* TXFCSErrors port 1, bits 15:0 */ #define RM9000_GE_TX_FCS_ERRORS_LOW_PORT_2 0x28a0 /* TXFCSErrors port 2, bits 15:0 */ #define RM9000_GE_TX_FCS_ERRORS_MID_PORT_0 0x08a4 /* TXFCSErrors port 0, bits 31:16 */ #define RM9000_GE_TX_FCS_ERRORS_MID_PORT_1 0x18a4 /* TXFCSErrors port 1, bits 31:16 */ #define RM9000_GE_TX_FCS_ERRORS_MID_PORT_2 0x28a4 /* TXFCSErrors port 2, bits 31:16 */ #define RM9000_GE_TX_FCS_ERRORS_HIGH_PORT_0 0x08a8 /* TXFCSErrors port 0, bits 39:32 */ #define RM9000_GE_TX_FCS_ERRORS_HIGH_PORT_1 0x18a8 /* TXFCSErrors port 1, bits 39:32 */ #define RM9000_GE_TX_FCS_ERRORS_HIGH_PORT_2 0x28a8 /* TXFCSErrors port 2, bits 39:32 */ #endif /* !defined(_RM9000_MAC_H_) */