/* * Copyright (c) 2004 PMC-Sierra, Inc. (www.pmc-sierra.com) * RM9200 register additions: brad_larson@pmc-sierra.com * Copyright (c) 2003 Opsycon AB (www.opsycon.se) * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Opsycon AB. * This product includes software developed by PMC-Sierra Inc. * 4. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #if !defined(_RM9000_REG_H_) #define _RM9000_REG_H_ /* * CPU control registers */ #define RM9000_OCD_INFO 0x0000 /* OCD info */ #define RM9000_RESET_STAT 0x0a20 /* Reset status */ #define RM9000_RESET_SET 0x0a24 /* Reset set */ #define RM9000_RESET_CLR 0x0a28 /* Reset clear */ #define RM9000_UPENR 0x00f0 /* Microprocessor peripheral enable */ /* * Semaphore register */ #define RM9000_SEM 0x0a60 #define RM9000_SEMSET 0x0a64 #define RM9000_SEMCLR 0x0a68 /* * SDRAM, local bus, and hypertransport region control registers */ #define RM9000_LKB0 0x0100 #define RM9000_LKB0_MAIN 0x0038 #define RM9000_LKB1 0x0108 #define RM9000_LKM1 0x010c #define RM9000_LKB2 0x0110 #define RM9000_LKM2 0x0114 #define RM9000_LKB3 0x0118 #define RM9000_LKM3 0x011c #define RM9000_LKB4 0x0120 #define RM9000_LKM4 0x0124 #define RM9000_LKB5 0x0128 #define RM9000_LKM5 0x012c #define RM9000_LKB6 0x0130 #define RM9000_LKM6 0x0134 #define RM9000_LKB7 0x0138 #define RM9000_LKM7 0x013c #define RM9000_LKB8 0x0140 #define RM9000_LKM8 0x0144 #define RM9000_LKB9 0x0148 #define RM9000_LKM9 0x014c #define RM9000_LKB10 0x0150 #define RM9000_LKM10 0x0154 #define RM9000_LKB11 0x0158 #define RM9000_LKM11 0x015c #define RM9000_LKB12 0x0160 #define RM9000_LKM12 0x0164 #define RM9000_LKB13 0x0168 #define RM9000_LKM13 0x016c #define RM9000_LDP0 0x0200 #define RM9000_LDP1 0x0210 #define RM9000_LDP2 0x0220 #define RM9000_LDP3 0x0230 #define RM9000_SDRAM_CONFIG 0x0300 #define RM9000_SDRAM_MODE 0x0304 #define RM9000_RANK0_TIMING 0x0344 #define RM9000_RANK1_TIMING 0x0354 #define RM9000_RANK2_TIMING 0x0364 #define RM9000_RANK3_TIMING 0x0374 #define RM9000_RANK0_CONFIG 0x0340 #define RM9000_RANK1_CONFIG 0x0350 #define RM9000_RANK2_CONFIG 0x0360 #define RM9000_RANK3_CONFIG 0x0370 /* * SCMB subsystem */ #define RM9000_SCMB_0_CONTROL 0x0180 /* SCMB 0 Control */ #define RM9000_SCMB_0_CLKA 0x0184 /* SCMB 0 Clock A */ #define RM9000_SCMB_0_CLKB 0x0188 /* SCMB 0 Clock B */ #define RM9000_MDIO_0_COMMAND 0x0190 /* MDIO 0 Command */ #define RM9000_MDIO_0_DEVICE_PORT_ADDRESS 0x0194 /* MDIO 0 Device and Port addrs */ #define RM9000_MDIO_0_DATA 0x0198 /* MDIO 0 Data */ #define RM9000_MDIO_0_INTERRUPTS 0x019c /* MDIO 0 Interrupts */ #define RM9000_2BI_0_CONFIG 0x01a0 /* 2BI 0 Configuration */ #define RM9000_2BI_0_COMMAND 0x01a4 /* 2BI 0 Command */ #define RM9000_2BI_0_ADDRESS 0x01a8 /* 2BI 0 Address */ #define RM9000_2BI_0_DATA0 0x01ac /* 2BI 0 Data bits 15:0 */ #define RM9000_2BI_0_DATA1 0x01b0 /* 2BI 0 Data bits 31:16 */ #define RM9000_2BI_0_DATA2 0x01b4 /* 2BI 0 Data bits 47:32 */ #define RM9000_2BI_0_DATA3 0x01b8 /* 2BI 0 Data bits 63:48 */ #define RM9000_2BI_0_INTERRUPTS 0x01bc /* 2BI 0 Interrupts */ #define RM9000_SCMB_1_CONTROL 0x01c0 /* SCMB 1 Control */ #define RM9000_SCMB_1_CLKA 0x01c4 /* SCMB 1 Clock A */ #define RM9000_SCMB_1_CLKB 0x01c8 /* SCMB 1 Clock B */ #define RM9000_MDIO_1_COMMAND 0x01d0 /* MDIO 1 Command */ #define RM9000_MDIO_1_DEVICE_PORT_ADDRESS 0x01d4 /* MDIO 1 Device and Port addrs */ #define RM9000_MDIO_1_DATA 0x01d8 /* MDIO 1 Data */ #define RM9000_MDIO_1_INTERRUPTS 0x01dc /* MDIO 1 Interrupts */ #define RM9000_2BI_1_CONFIG 0x01e0 /* 2BI 1 Configuration */ #define RM9000_2BI_1_COMMAND 0x01e4 /* 2BI 1 Command */ #define RM9000_2BI_1_ADDRESS 0x01e8 /* 2BI 1 Address */ #define RM9000_2BI_1_DATA0 0x01ec /* 2BI 1 Data bits 15:0 */ #define RM9000_2BI_1_DATA1 0x01f0 /* 2BI 1 Data bits 31:16 */ #define RM9000_2BI_1_DATA2 0x01f4 /* 2BI 1 Data bits 47:32 */ #define RM9000_2BI_1_DATA3 0x01f8 /* 2BI 1 Data bits 63:48 */ #define RM9000_2BI_1_INTERRUPTS 0x01fc /* 2BI 1 Interrupts */ /* * MII registers */ #define RM9000_PHY_AUTONEG_ADV 0x0004 #define RM9000_PHY_LP_ABILITY 0x0005 #define RM9000_MDIO_MII_CTRL 0x0009 #define RM9000_MDIO_MII_EXTENDED 0x000f #define RM9000_MDIO_PHY_CTRL 0x0010 #define RM9000_MDIO_PHY_STATUS 0x0011 #define RM9000_MDIO_PHY_IE 0x0012 #define RM9000_MDIO_PHY_IS 0x0013 #define RM9000_MDIO_PHY_LED 0x0018 #define RM9000_MDIO_PHY_LED_OVER 0x0019 #endif /* !defined(_RM9000_REG_H_) */