/*
 * Copyright (c) 2003, 2004 PMC-Sierra, Inc. (www.pmc-sierra.com)
 * Author : Brad Larson (brad_larson@pmc-sierra.com)
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *      This product includes software developed by PMC-Sierra, Inc.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */
#ifndef _IF_RME_H
#define _IF_RME_H

#include <target/pmon_target.h>

#define	RM9220_GE_DEVICE_ID	0x9220

/* Keep the ring sizes a power of two for efficiency */
#define TX_RING_SIZE    64	
#define RX_RING_SIZE	64	
#define RX_BUF_SIZE	1536	/* Size of each temporary Rx buffer */
#define TX_BUF_SIZE	1536	/* Size of each temporary Tx buffer */

/*
 *  Tx descriptor definitions
 */
typedef struct {
    uint16_t cmdstat;
    uint16_t buf_len;
    uint32_t buf_ptr;
} TX_DESC;

/*
 *  Rx descriptor definitions
 */
typedef struct {
    uint32_t dummy;
    uint32_t cpu_buf_ptr;
    uint32_t cmdstat;
    uint32_t xdma_buf_ptr;
} RX_DESC;

/* Rx descriptor command and status */
#define	RX_CRC_ERROR		(1<<27)	        /* crc error */
#define	RX_OVERFLOW_ERROR	(1<<15)	        /* overflow */
#define RX_BUFFER_OWNED	        (1<<21)	        /* buffer ownership */
#define	RX_STP			(1<<31)	        /* start of packet */
#define	RX_BAM			(1<<30)	        /* broadcast address match */
#define RX_PAM			(1<<28)	        /* physical address match */
#define RX_LAFM	        	(1<<29)	        /* logical address filter match */
#define RX_VLAN		        (1<<26)	        /* virtual lans */
#define RX_PERR		        (1<<19)	        /* packet error */
#define RX_TRUNC		(1<<20)	        /* packet size greater than 32 buffers */

/* Tx descriptor command */
#define	TX_BUFFER_OWNED	        (1<<5)	        /* buffer ownership */	
#define	TX_ENABLE_INTERRUPT	(1<<15)	        /* interrupt enable */
#define	ONE_BUFFER		0x1	        /* buffer count */

/* MII/GMII definitions */
#define RM9000_GMII_MODE      	0x1
#define RM9000_HALF_DUPLEX      (0x1 << 12)
#define RM9000_LINK_SPEED_100   (0x1 << 8)
#define RM9000_LINK_SPEED_1000  (0x1 << 9)

/* PHY definitions */
#define PHY_CONTROL_REG 0x0
#define PHY_STATUS_REG  0x1
#define PHY_SPECIFIC_STATUS_REG 0x11

/* Interrupt definitions */
#define XDMA_RX_CH0_INT         0x1
#define XDMA_TX_CH0_INT         (0x1 << 1)
#define XDMA_RX_CH4_INT         (0x1 << 8)
#define XDMA_TX_CH4_INT         (0x1 << 9)
#define XDMA_RX_CH8_INT         (0x1 << 16)
#define XDMA_TX_CH8_INT         (0x1 << 17)

/* Device control block */
struct rme_softc {
	struct device	sc_dev;		/* Generic device structures */
	void		*sc_ih;		/* Interrupt handler cookie */
	bus_space_tag_t	sc_st;		/* Bus space tag */
	bus_space_handle_t sc_sh;	/* Bus space handle */
	pci_chipset_tag_t sc_pc;	/* Chipset handle needed by mips */
	struct arpcom	arpcom;		/* Per interface network data */
	struct mii_data mii_data;
	RX_DESC		*rx_ring;
	TX_DESC		*tx_ring;
	u_int32_t	*rx_hash;
	int		sc_port;	/* Easy access port number */
	int 		hash_mode;
        u_int8_t  	*tx_buf;
        u_int8_t	*rx_buf;

        int rx_queued;
        int rx_perr;			/* Packets with PERR bit set */
        int rx_no_stp;			/* Packets missing start of packet bit (STP) */
        int rx_next_out;	       	/* The next free ring entry to receive */
   	int rx_skipped;			/* Receive xdma descriptor skipped */ 
        int nextTxDesc;	  		/* The last ring entry the ISR processed */
        int tx_queued;
        int tx_full;        	       	/* Tx ring is full */
        //mib_counters_t mib;
        //struct net_device_stats stats;

        int chip_rev;
        int phy_addr; 		       	/* PHY address */
        unsigned char phys[2]; 	       	/* MII device addresses */
};

/*
 *  External prototypes
 */

/* MII access functions */
int  rme_mii_read (int phyaddr, int regaddr);
void rme_mii_write (int phyaddr, int regaddr, int data);

#endif /* _IF_RME_H_ */