/*	$OpenBSD$ */

/*
 * Copyright (c) 2001 Opsycon AB  (www.opsycon.se)
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed by Opsycon AB, Sweden.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */

#ifndef _JAGUAR_ATX_H_
#define _JAGUAR_ATX_H_

#include <machine/endian.h>

/*
 *  Mapping
 */
#define	IO_OFFSET		0x40000000
#define	PHYS_TO_IOSPACE(x)	(PHYS_TO_UNCACHED(x) + IO_OFFSET)

/*
 *  Define top of PMON-land. PMON will not use memory above this
 *  address but leave it alone for applications.
 */
//#define	PMON_TOP		0x00200000	/* 2MB */

/*
 *  Galileo CS space mapping.
 */
#define	FPGA_BASE		PHYS_TO_IOSPACE(0x1c000000)
#define	FPGA_SIZE		0x00800000
#define	RTC_BASE		PHYS_TO_IOSPACE(0x1c800000)
#define	RTC_SIZE		0x00800000
#define	UART_BASE		PHYS_TO_IOSPACE(0x1d000000)
#define	UART_SIZE		0x01000000
#define	FLASH_BASE		PHYS_TO_IOSPACE(0x1f000000)
#define	FLASH_SIZE		0x00c00000
#define	BOOT_BASE		PHYS_TO_IOSPACE(0x1fc00000)
#define	BOOT_SIZE		0x00400000

/*
 * Galileo Internal SRAM mapping
 */

#define OC_SRAM_BASE		PHYS_TO_IOSPACE(0x1e000000)
#define OC_SRAM_SIZE		0x00040000

/*
 *  Galileo PCI Bus allocation
 */
#define PCI0_MEM_SPACE_BASE     0xffffffffc0000000LL
#define PCI0_MEM_SPACE_SIZE     0x10000000
#define PCI0_IO_SPACE_BASE      0xffffffffe0000000LL
#define PCI0_IO_SPACE_SIZE      0x08000000

#define PCI1_MEM_SPACE_BASE     0xffffffffd0000000LL
#define PCI1_MEM_SPACE_SIZE     0x10000000
#define PCI1_IO_SPACE_BASE      0xffffffffe8000000LL
#define PCI1_IO_SPACE_SIZE      0x08000000

#if defined(A64)
#define	GT_MAXPHYS		0x0000ffff	/* Max phys address bits - 16 */
#else
#define	GT_MAXPHYS		0x0000ffff	/* Max phys address bits - 16 */
#endif

/* 
 *  Hyper Transport on RM9K (looks like a PCI bus)
 */
#define PCI2_MEM_SPACE_BASE     0x18000000
#define PCI2_MEM_SPACE_SIZE     0x01000000
#define PCI2_IO_SPACE_BASE      0x19000000
#define PCI2_IO_SPACE_SIZE      0x01000000

#define	ISA_IO_BASE		PCI_IO_BASE

/*
 *  Packet buffer RAM on RM9K.
 */
#define	PKT_SRAM_BASE		0x1a000000
#define	PKT_SRAM_SIZE		0x00002000

/*
 *  Bootrom parameters
 */
#define	BOOTROM_BASE	0xfc00000
#define	BOOTROM_SIZE	(1024 * 512)

/*
 *  Timekeeper/NVRAM (M48T37)
 */
#define NVRAM_BASE_ADDR         RTC_BASE
#define NVRAM_SIZE              (0x7ff0)
#define NVRAM_BASE              NVRAM_BASE_ADDR
#define NVRAM_FIRST_ENV         (NVRAM_BASE + 0x0000)
#define NVRAM_LAST_ENV          (NVRAM_BASE + 0x77ff)
#define NVRAM_SIZE_ENV          (NVRAM_LAST_ENV - NVRAM_FIRST_ENV + 1)
#define NVRAM_VXWORKS           (NVRAM_BASE + NVRAM_SIZE - 512)
#define NVRAM_VXWORKS_DEFAULT \
"dc(0,0)host:/usr/vw/config/ev64340/vxWorks h=90.0.0.3 e=90.0.0.50 u=target"
#define NVRAM_ENETADDR          (NVRAM_BASE + 0x7cf2)

#define M48T37_BASE             (NVRAM_BASE_ADDR + NVRAM_SIZE)

/*
 *  Device module duart I/O ports.
 */
#define COM1_BASE_ADDR	(UART_BASE + 0x20)	/* Com 1 */
#define COM2_BASE_ADDR	(UART_BASE + 0x00)	/* Com 2 */

#define	NS16550HZ	20000000
#if BYTE_ORDER == LITTLE_ENDIAN
#define nsreg(x)	unsigned char CAT(pad_,x)[3]; unsigned char x;
#define NSREG(x)	((x) * 4 + 3)
#elif BYTE_ORDER == BIG_ENDIAN
#define nsreg(x)	unsigned char x; unsigned char CAT(pad_,x)[3];
#define NSREG(x)	((x) * 4)
#else
#error BYTE_ORDER is neither BIG_ENDIAN or LITTLE_ENDIAN
#endif

/*
 *  Device module discouart defs.
 */
#define	GTSYSCLK	100000000	/* Sysclock HZ */

#define	RM9K_BASE_ADDR		PHYS_TO_UNCACHED(0x1b000000)
#define	RM9K_WRITE(ofs, data) \
   *(volatile u_int32_t *)(RM9K_BASE_ADDR+ofs) = data
#define	RM9K_READ(ofs) \
   *(volatile u_int32_t *)(RM9K_BASE_ADDR+ofs)

/*
 *  Define how to test for non-dmaable address range.
 */
#if !defined(_LOCORE)
extern paddr_t dma_start, dma_end;
#endif

#define	IS_DMA_ABLE(addr) \
	(VA_TO_PA(addr) >= dma_start && VA_TO_PA(addr) <= dma_end)

#endif /* _JAGUAR_ATX_H_ */