/* $Id: pci_machdep.c,v 1.1.1.1 2006/08/23 17:03:02 pefo Exp $ */ /* * Copyright (c) 2001 Opsycon AB (www.opsycon.se) * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Opsycon AB, Sweden. * 4. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #include #include #include #include #include #include #include #include #include "include/jaguar_atx.h" #include "pmon/dev/mv64340reg.h" #include extern void *pmalloc (size_t); extern int read32_or_trap(int32_t *); /* PCI i/o regions in PCI space */ #define PCI_IO_SPACE_PCI_BASE 0x00000000 /* PCI mem regions in PCI space */ #define PCI_LOCAL_MEM_PCI_BASE 0x00000000 /* CPU Mem accessed from PCI */ /* soft versions of above */ static pcireg_t pci_local_mem_pci_base; static pcireg_t _pci_conf_readn __P((pcitag_t, int, int)); static void _pci_conf_writen __P((pcitag_t, int, pcireg_t, int)); extern int _pciverbose; extern char hwethadr[6]; struct pci_bus *_pci_bus[16]; int _max_pci_bus = 0; int hypertransport_enable; struct bartab { int scslow, scssize; int pci0size, pci1size; int barh, barl; } barlist[] = { { SCS_0_BASE_ADDRESS, SCS_0_SIZE, PCI_0SCS_0_BANK_SIZE, PCI_1SCS_0_BANK_SIZE, PCI_SCS_0_BASE_ADDRESS_HIGH, PCI_SCS_0_BASE_ADDRESS_LOW }, { SCS_1_BASE_ADDRESS, SCS_1_SIZE, PCI_0SCS_1_BANK_SIZE, PCI_1SCS_1_BANK_SIZE, PCI_SCS_1_BASE_ADDRESS_HIGH, PCI_SCS_1_BASE_ADDRESS_LOW }, { SCS_2_BASE_ADDRESS, SCS_2_SIZE, PCI_0SCS_2_BANK_SIZE, PCI_1SCS_2_BANK_SIZE, PCI_SCS_2_BASE_ADDRESS_HIGH, PCI_SCS_2_BASE_ADDRESS_LOW }, { SCS_3_BASE_ADDRESS, SCS_3_SIZE, PCI_0SCS_3_BANK_SIZE, PCI_1SCS_3_BANK_SIZE, PCI_SCS_3_BASE_ADDRESS_HIGH, PCI_SCS_3_BASE_ADDRESS_LOW }, }; #define NBARS (sizeof(barlist) / sizeof(struct bartab)) /* * Called to initialise the bridge at the beginning of time */ int _pci_hwinit (initialise, iot, memt) int initialise; bus_space_tag_t iot; bus_space_tag_t memt; { pcireg_t stat; struct pci_device *pcidev; struct pci_bus *pcibus; int i; pcitag_t tag; /* * PCI and local bus maps 1-1 */ iot->bus_base = (long)~0xffffffffLL; iot->bus_reverse = 1; memt->bus_base = (long)~0xffffffffLL; memt->bus_reverse = 1; /* * Where local memory starts seen from PCI. */ pci_local_mem_pci_base = PCI_LOCAL_MEM_PCI_BASE; if (!initialise) { return(0); } /* * Allocate and initialize PCI bus heads. */ /* * PCI Bus 0 */ pcidev = pmalloc(sizeof(struct pci_device)); pcibus = pmalloc(sizeof(struct pci_bus)); if(pcidev == NULL || pcibus == NULL) { printf("pci: can't alloc memory. pci not initialized\n"); return(-1); } pcidev->pa.pa_bus = 0; pcidev->pa.pa_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; pcidev->pa.pa_iot = iot; pcidev->pa.pa_memt = memt; pcidev->pa.pa_dmat = &bus_dmamap_tag; pcidev->bridge.secbus = pcibus; _pci_head = pcidev; pcibus->minpcimemaddr = (long)PCI0_MEM_SPACE_BASE; pcibus->nextpcimemaddr = (long)PCI0_MEM_SPACE_BASE+PCI0_MEM_SPACE_SIZE; pcibus->minpciioaddr = (long)PCI0_IO_SPACE_BASE; pcibus->nextpciioaddr = (long)PCI0_IO_SPACE_BASE+PCI0_IO_SPACE_SIZE; pcibus->pci_mem_base = (long)PCI0_MEM_SPACE_BASE; /* Maps 1-1 */ pcibus->pci_io_base = (long)PCI0_IO_SPACE_BASE; /* Maps 1-1 */ pcibus->max_lat = 255; pcibus->fast_b2b = 1; pcibus->prefetch = 1; pcibus->bandwidth = 4000000; pcibus->ndev = 1; _pci_bushead = pcibus; _pci_bus[_max_pci_bus++] = pcibus; register_mem((void *)PCI0_MEM_SPACE_BASE, (void *)PCI0_MEM_SPACE_BASE+PCI0_MEM_SPACE_SIZE-1, MEM_IO, "PCI 0 memory"); register_mem((void *)PCI0_IO_SPACE_BASE, (void *)PCI0_IO_SPACE_BASE+PCI0_IO_SPACE_SIZE-1, MEM_IO, "PCI 0 I/O"); /* * PCI Bus 1 */ pcidev = pmalloc(sizeof(struct pci_device)); pcibus = pmalloc(sizeof(struct pci_bus)); if(pcidev == NULL || pcibus == NULL) { printf("pci: can't alloc memory. pci 1 not initialized\n"); return(-1); } *pcidev = *_pci_head; pcidev->pa.pa_bus = 1; pcidev->bridge.secbus = pcibus; _pci_head->next = pcidev; *pcibus = *_pci_bushead; pcibus->minpcimemaddr = (long)PCI1_MEM_SPACE_BASE; pcibus->nextpcimemaddr = (long)PCI1_MEM_SPACE_BASE+PCI1_MEM_SPACE_SIZE; pcibus->minpciioaddr = (long)PCI1_IO_SPACE_BASE; pcibus->nextpciioaddr = (long)PCI1_IO_SPACE_BASE+PCI1_IO_SPACE_SIZE; pcibus->pci_mem_base = (long)PCI1_MEM_SPACE_BASE; /* Maps 1-1 */ pcibus->pci_io_base = (long)PCI1_IO_SPACE_BASE; /* Maps 1-1 */ _pci_bushead->next = pcibus; _pci_bus[_max_pci_bus++] = pcibus; register_mem((void *)PCI1_MEM_SPACE_BASE, (void *)PCI1_MEM_SPACE_BASE+PCI1_MEM_SPACE_SIZE-1, MEM_IO, "PCI 1 memory"); register_mem((void *)PCI1_IO_SPACE_BASE, (void *)PCI1_IO_SPACE_BASE+PCI1_IO_SPACE_SIZE-1, MEM_IO, "PCI 1 I/O"); /* * PCI Bus 2 (HyperTransport) */ pcidev = pmalloc(sizeof(struct pci_device)); pcibus = pmalloc(sizeof(struct pci_bus)); if(pcidev == NULL || pcibus == NULL) { printf("pci: can't alloc memory. pci 2 not initialized\n"); return(-1); } *pcidev = *_pci_head->next; pcidev->pa.pa_bus = 2; pcidev->pa.pa_iot = pmalloc(sizeof(struct tgt_bus_space)); pcidev->pa.pa_memt = pmalloc(sizeof(struct tgt_bus_space)); pcidev->pa.pa_iot->bus_base = (long)UNCACHED_MEMORY_ADDR; pcidev->pa.pa_iot->bus_reverse = 1; pcidev->pa.pa_memt->bus_base = (long)UNCACHED_MEMORY_ADDR; pcidev->pa.pa_memt->bus_reverse = 1; pcidev->bridge.secbus = pcibus; _pci_head->next->next = pcidev; *pcibus = *_pci_bushead->next; pcibus->minpcimemaddr = PCI2_MEM_SPACE_BASE; pcibus->nextpcimemaddr = PCI2_MEM_SPACE_BASE + PCI2_MEM_SPACE_SIZE; pcibus->minpciioaddr = PCI2_IO_SPACE_BASE; pcibus->nextpciioaddr = PCI2_IO_SPACE_BASE + PCI2_IO_SPACE_SIZE; pcibus->pci_mem_base = PCI2_MEM_SPACE_BASE; /* Maps 1-1 */ pcibus->pci_io_base = PCI2_IO_SPACE_BASE; /* Maps 1-1 */ _pci_bushead->next->next = pcibus; _pci_bus[_max_pci_bus++] = pcibus; register_mem((void *)PCI2_MEM_SPACE_BASE, (void *)PCI2_IO_SPACE_BASE + PCI2_IO_SPACE_SIZE - 1, MEM_IO, "Hyper Transport"); register_mem((void *)PCI2_MEM_SPACE_BASE, (void *)PCI2_MEM_SPACE_BASE + PCI2_MEM_SPACE_SIZE - 1, MEM_IO, "memory"); register_mem((void *)PCI2_IO_SPACE_BASE, (void *)PCI2_IO_SPACE_BASE + PCI2_IO_SPACE_SIZE - 1, MEM_IO, "I/O"); /* * Program bus numbers */ GT_WRITE(PCI_0P2P_CONFIGURATION, 0x000000ff); GT_WRITE(PCI_1P2P_CONFIGURATION, 0x000100ff); /* * Enable PCI 0 as master to do config cycles. */ stat = _pci_conf_read(_pci_make_tag(0, 0, 0), PCI_COMMAND_STATUS_REG); stat |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE; _pci_conf_write(_pci_make_tag(0, 0, 0), PCI_COMMAND_STATUS_REG, stat); /* * Enable PCI 1 as master to do config cycles. */ stat = _pci_conf_read(_pci_make_tag(1, 0, 0), PCI_COMMAND_STATUS_REG); stat |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE; _pci_conf_write(_pci_make_tag(1, 0, 0), PCI_COMMAND_STATUS_REG, stat); /* * Enable HT interface as master to do config cycles. */ hypertransport_enable = 0; /* Wait for HW init to complete */ for (i = 0; i < 10000; i++) if (RM9K_READ(0x644) & (1<<5)) break; if (!getenv("noht") && RM9K_READ(0x644) & (1<<5)) { /* Assume for the moment that this works... */ hypertransport_enable = 1; RM9K_WRITE(0x604, 6); /* enable master */ /* SW workaround for RM9000x2 1.0 errata * Limit how many tranx can be accepted by softmacro on RX * link. This will not be necessary for 2.0 */ RM9K_WRITE(0x66c, (1<<12) | (1<<10) | (1<<8) | 1); /* If we were going to change link speed, we'd do it here */ /* Reset the link for errata and speed change */ RM9K_WRITE(0x644, RM9K_READ(0x644) | (1<<15)); RM9K_READ(0x644); for (i = 0; i < 100000; i++) RM9K_READ(0x644); /* Turn off reset */ RM9K_WRITE(0x644, RM9K_READ(0x644) & 0xffff7fff); RM9K_READ(0x644); for (i = 0; i < 100000; i++) RM9K_READ(0x644); /* Wait for HW init to complete */ for (i = 0; i < 10000000; i++) if (RM9K_READ(0x644) & (1<<5)) break; /* Enable the master again */ RM9K_WRITE(0x604, 6); /* If the INIT is off, we have a problem. Neuter the bus. */ if (!(RM9K_READ(0x644) & (1<<5))) hypertransport_enable = 0; } /* * Set up CPU to PCI mappings. Use only one I/O and MEM each. */ GT_WRITE(PCI_0I_O_BASE_ADDRESS, GT_BARVALUE(PCI0_IO_SPACE_BASE)); GT_WRITE(PCI_0I_O_SIZE, (PCI0_IO_SPACE_SIZE - 1) >> 16); GT_WRITE(PCI_0MEMORY0_BASE_ADDRESS, GT_BARVALUE(PCI0_MEM_SPACE_BASE)); GT_WRITE(PCI_0MEMORY0_SIZE, (PCI0_MEM_SPACE_SIZE - 1) >> 16); GT_WRITE(PCI_1I_O_BASE_ADDRESS, GT_BARVALUE(PCI1_IO_SPACE_BASE)); GT_WRITE(PCI_1I_O_SIZE, (PCI1_IO_SPACE_SIZE - 1) >> 16); GT_WRITE(PCI_1MEMORY0_BASE_ADDRESS, GT_BARVALUE(PCI1_MEM_SPACE_BASE)); GT_WRITE(PCI_1MEMORY0_SIZE, (PCI1_MEM_SPACE_SIZE - 1) >> 16); /* PCI 2 -- Hypertransport interface */ if (hypertransport_enable) { /* LKB7/LKM7 is I/O */ /* LKB8/LKM8 is MEM */ RM9K_WRITE(0x138, (PCI2_IO_SPACE_BASE >> 4) | 1); RM9K_WRITE(0x13c, ((PCI2_IO_SPACE_SIZE / 4096) - 1) << 8); RM9K_WRITE(0x140, (PCI2_MEM_SPACE_BASE >> 4) | 1); RM9K_WRITE(0x144, ((PCI2_MEM_SPACE_SIZE / 4096) - 1) << 8); #if BYTE_ORDER == BIG_ENDIAN /* Undocumented byte swap bit */ RM9K_WRITE(0x0f4, 0x10000); #endif } /* The HT spec requires us to assign host IDs (ala devnum) to each * device on the chain. We do that via a simple probing mechanism * which works because devices power-up with address 0 and don't * interfere with each other at that address (the beauty of a chain * architecture as opposed to a true bus). */ if (hypertransport_enable) { /* loop and assign addresses */ for (i = 1; ; i++) { if(i == 2) break; /* send a TX to inform the slave of upstream dir */ RM9K_WRITE(0x6f8, 0x80000000); RM9K_WRITE(0x6fc, 0x80000000); /* get reg 0x48 -- look for CRC errors on far link */ RM9K_WRITE(0x6f8, 0x80000048); if (read32_or_trap((int32_t *)(RM9K_BASE_ADDR+0x6fc))) break; if (RM9K_READ(0x6fc) & 0xf00) break; /* we found a device! -- set the address */ RM9K_WRITE(0x6f8, 0x80000040); RM9K_WRITE(0x6fc, i << 16); } /* select the last device on the chain */ RM9K_WRITE(0x6f8, ((i-1)<<11) | 0x80000048); /* get the HTLink register */ stat = RM9K_READ(0x6fc); /* set end-of-chain bit */ stat |= 1 << 6; /* write and readback to force a posting */ RM9K_WRITE(0x6fc, stat); stat = RM9K_READ(0x6fc); /* set 'transmit off' bit */ stat |= 1 << 7; /* write and readback to force a posting */ RM9K_WRITE(0x6fc, stat); stat = RM9K_READ(0x6fc); } /* * Set up mapping for PCI to localmem accesses. * config regs to find mapping and size. BAR and * size register should be set to match SDRAM SCS. * We use PCI0 I/O and PCI0 MEM0. Same for PCI1. */ stat = GT_READ(CPU_BASE_ADDRESS_ENABLE); stat |= (1<<11) | (1<<12) | (1<<13) | (1<<16) | (1<<17) | (1<<18); stat &= ~((1<<9) | (1<<10) | (1<<14) | (1<<15)); GT_WRITE(CPU_BASE_ADDRESS_ENABLE, stat); if (hypertransport_enable) { RM9K_WRITE(0x610, 6); /* HTBAR0 */ RM9K_WRITE(0x688, 0xffff); /* HTMASK0 */ } for(i = 0; i < NBARS; i++) { u_int32_t baselo, basesize; baselo = GT_READ(barlist[i].scslow) << 16; basesize = (GT_READ(barlist[i].scssize) + 1) << 16; basesize = -1; /* bus 0 */ tag = _pci_make_tag(0, 0, (barlist[i].barl & 0x700) >> 8); stat = _pci_conf_read(tag, barlist[i].barl & 0xff) & 0xffff; stat |= baselo & 0xfffff000; _pci_conf_write(tag, barlist[i].barl & 0xff, stat); _pci_conf_write(tag, barlist[i].barh & 0xff, 0); /* bus 1 */ tag = _pci_make_tag(1, 0, (barlist[i].barl & 0x700) >> 8); stat = _pci_conf_read(tag, barlist[i].barl & 0xff) & 0xffff; stat |= baselo & 0xfffff000; _pci_conf_write(tag, barlist[i].barl & 0xff, stat); _pci_conf_write(tag, barlist[i].barh & 0xff, 0); /* set size registers */ GT_WRITE(barlist[i].pci0size, basesize & 0xfffff000); GT_WRITE(barlist[i].pci1size, basesize & 0xfffff000); } /* Configure the Internal Registers decode space */ /* bus 0 */ tag = _pci_make_tag(0, 0, 0); stat = _pci_conf_read(tag, PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS) & 0xffff; stat |= GT_BASE_ADDR & 0xfffff000; _pci_conf_write(tag, PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, stat); /* bus 1 */ tag = _pci_make_tag(1, 0, 0); stat = _pci_conf_read(tag, PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS) & 0xffff; stat |= GT_BASE_ADDR & 0xfffff000; _pci_conf_write(tag, PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, stat); /* enable the PCI slave windows we want */ stat = GT_READ(PCI_0BASE_ADDRESS_REGISTERS_ENABLE); stat |= GT_READ(CPU_BASE_ADDRESS_ENABLE) & 0x07ff; GT_WRITE(PCI_0BASE_ADDRESS_REGISTERS_ENABLE, stat); stat = GT_READ(PCI_1BASE_ADDRESS_REGISTERS_ENABLE); stat |= GT_READ(CPU_BASE_ADDRESS_ENABLE) & 0x07ff; GT_WRITE(PCI_1BASE_ADDRESS_REGISTERS_ENABLE, stat); return(3); } /* * Called to reinitialise the bridge after we've scanned each PCI device * and know what is possible. We also set up the interrupt controller * routing and level control registers. */ void _pci_hwreinit (void) { } void _pci_flush (void) { } /* * Map the CPU virtual address of an area of local memory to a PCI * address that can be used by a PCI bus master to access it. */ vm_offset_t _pci_dmamap(va, len) vm_offset_t va; unsigned int len; { return(pci_local_mem_pci_base + VA_TO_PA (va)); } /* * Map the PCI address of an area of local memory to a CPU physical * address. */ vm_offset_t _pci_cpumap(pcia, len) vm_offset_t pcia; unsigned int len; { return PA_TO_VA(pcia - pci_local_mem_pci_base); } /* * Make pci tag from bus, device and function data. */ pcitag_t _pci_make_tag(bus, device, function) int bus; int device; int function; { pcitag_t tag; tag = (bus << 16) | (device << 11) | (function << 8); return(tag); } /* * Break up a pci tag to bus, device function components. */ void _pci_break_tag(tag, busp, devicep, functionp) pcitag_t tag; int *busp; int *devicep; int *functionp; { if (busp) { *busp = (tag >> 16) & 255; } if (devicep) { *devicep = (tag >> 11) & 31; } if (functionp) { *functionp = (tag >> 8) & 7; } } int _pci_canscan (pcitag_t tag) { int bus, device, function; _pci_break_tag (tag, &bus, &device, &function); if(device == 0) { return(0); /* Ignore the Discovery and HT host itself */ } return (1); } /* * Read a value form PCI configuration space. Support for * all three data sizes (byte, halfword and word) is provided. */ static pcireg_t _pci_conf_readn(tag, reg, width) pcitag_t tag; int reg; int width; { pcireg_t data; u_int32_t adr; int bus, device, function; if (reg & (width-1) || reg < 0 || reg >= 0x100) { if (_pciverbose >= 1) { _pci_tagprintf (tag, "_pci_conf_read: bad reg 0x%x\r\n", reg); } return ~0; } _pci_break_tag (tag, &bus, &device, &function); /* Type 0 configuration on onboard PCI bus */ if (device > 29 || function > 7) { return ~0; /* device out of range */ } adr = (bus << 16) | (device << 11) | (function << 8) | reg | GT_IPCI_CFGADDR_ConfigEn; /* * PLX HT7520 daughtercard does not claim config accesses to * unimplemented functions and forwards to the other side of * the tunnel which hangs the HT interface. This is a simple * way to avoid the problem. */ if (bus > 1 && function > 1) return ~0; if (bus == 0) { GT_WRITE(PCI_0CONFIGURATION_ADDRESS, adr); data = GT_READ(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER); } else if (bus == 1 ) { GT_WRITE(PCI_1CONFIGURATION_ADDRESS, adr); data = GT_READ(PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER); } else { if (!hypertransport_enable || device != 1) return ~0; /* HyperTransport */ /* determine if a Type 1 cycle is needed */ adr = (device << 11) | (function << 8) | reg | 0x80000000; if (bus != 2) { adr |= (bus << 16) | 1; } RM9K_WRITE(0x6f8, adr); if (read32_or_trap((int32_t *)(RM9K_BASE_ADDR+0x6fc))) data = ~0; else data = RM9K_READ(0x6fc); } return data; } pcireg_t _pci_conf_read(pcitag_t tag, int reg) { return _pci_conf_readn(tag, reg, 4); } /* * Write a value to PCI configuration space. */ static void _pci_conf_writen(tag, reg, data, width) pcitag_t tag; int reg; pcireg_t data; int width; { u_int32_t adr; int bus, device, function; if (reg & (width-1) || reg < 0 || reg >= 0x100) { if (_pciverbose >= 1) { _pci_tagprintf(tag, "_pci_conf_write: bad reg 0x%x\r\n", reg); } return; } _pci_break_tag (tag, &bus, &device, &function); /* Type 0 configuration on onboard PCI buses */ if (device > 29 || function > 7) { return; /* device out of range */ } adr = (bus << 16) | (device << 11) | (function << 8) | reg | GT_IPCI_CFGADDR_ConfigEn; if(bus == 0) { GT_WRITE(PCI_0CONFIGURATION_ADDRESS, adr); GT_WRITE(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, data); } else if (bus == 1) { GT_WRITE(PCI_1CONFIGURATION_ADDRESS, adr); GT_WRITE(PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER, data); } else { if (!hypertransport_enable) return; /* HyperTransport */ /* determine if a Type 1 cycle is needed */ adr = (device << 11) | (function << 8) | reg | 0x80000000; if (bus != 2) { adr |= (bus << 16) | 1; } RM9K_WRITE(0x6f8, adr); RM9K_WRITE(0x6fc, data); } } void _pci_conf_write(pcitag_t tag, int reg, pcireg_t data) { _pci_conf_writen (tag, reg, data, 4); } /* * Get contents of PCI Mapping register and do any machine * dependent mapping setup. */ int _pci_map_port(tag, reg, port) pcitag_t tag; int reg; unsigned int *port; { pcireg_t address; if (reg < PCI_MAPREG_START || reg >= PCI_MAPREG_END || (reg & 3)) { if (_pciverbose >= 1) { _pci_tagprintf(tag, "_pci_map_port: bad request\r\n"); } return -1; } address = _pci_conf_read(tag, reg); if (PCI_MAPREG_TYPE(address) != PCI_MAPREG_TYPE_IO) { if (_pciverbose >= 1) { _pci_tagprintf (tag, "_pci_map_port: attempt to i/o map a memory region\r\n"); } return(-1); } *port = (address & PCI_MAPREG_IO_ADDR_MASK) - PCI_IO_SPACE_PCI_BASE; return(0); } void * _pci_map_int(tag, level, func, arg) pcitag_t tag; int level; int (*func) __P((void *)); void *arg; { pcireg_t data; int pin, bus, device; data = _pci_conf_read(tag, PCI_INTERRUPT_REG); pin = PCI_INTERRUPT_PIN(data); if (pin == 0) { /* No IRQ used. */ return NULL; } if (pin > 4) { if (_pciverbose >= 1) { _pci_tagprintf (tag, "_pci_map_int: bad interrupt pin %d\r\n", pin); } return(NULL); } _pci_break_tag (tag, &bus, &device, NULL); if (bus != 0 || device > 5) { return(NULL); } /* XXX need to work this out based on device number etc. */ _pci_tagprintf(tag, "_pci_map_int: attempt to map device %d pin %c\n", device, '@' + pin); return(NULL); } void pci_sync_cache(p, adr, size, rw) void *p; vm_offset_t adr; size_t size; int rw; { CPU_IOFlushDCache(adr, size, rw); }