/* * Copyright (c) 2006 Opsycon AB (www.opsycon.se) * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #ifndef _MSP2200_H_ #define _MSP2200_H_ #include #include /* * Define top of PMON-land. PMON will not use memory above this * address but leave it alone for applications. */ //#define PMON_TOP 0x02000000 /* 32MB */ /* * Mapping */ #define ROM_BASE 0x00000000 #define RAM_BASE 0x10000000 #define GLOBAL_BASE 0x20000000 #define GPIO_BASE 0x21000000 #define UART_BASE 0x22000000 /* XXX Internal uart! */ #define TIMER_BASE 0x23000000 #define RTC_BASE 0x25000000 #define LPCREG_BASE 0x26000000 #define LPC_IO_BASE 0x27000000 #define WDTIMER_BASE 0x28000000 #define PCIREG_BASE 0x30000000 #define PCIIO_BASE 0x30000000 #define PCIMEM_BASE 0x40000000 #define FLASHREG_BASE 0x54000000 #define DRAMREG_BASE 0x55000000 /* XXX This mapping has to be revised when flash is available */ #if 0 #ifdef ENV_FLASH #define USERFLASH_BASE (FLASH_BASE+0x20000) /* Reserve first block for env */ #define USERFLASH_SIZE (FLASH_SIZE-0x20000) /* Flash in 68k space */ #else #define USERFLASH_BASE FLASH_BASE #define USERFLASH_SIZE FLASH_SIZE /* Flash in 68k space */ #endif #define BOOTFLASH_BASE 0x08000000 /* Boot flash in 68k space */ #define BOOTFLASH_SIZE 0x00080000 /* Boot flash in 68k space */ /* * Bootrom parameters used by "load -u". */ #define BOOTROM_BASE 0x00000000 #define BOOTROM_SIZE (1024 * 1024) #endif /* * PCI Bus allocation */ #define PCI_MEM_SPACE_BASE PCIMEM_BASE #define PCI_MEM_SPACE_SIZE 0x10000000 /* 128M */ #define PCI_IO_SPACE_BASE PCIIO_BASE #define PCI_IO_SPACE_SIZE 0x04000000 #define MSP2200_PCI_CONFIG_ADDR (PCI_IO_SPACE_BASE+0x28) #define MSP2200_PCI_CONFIG_DATA (PCI_IO_SPACE_BASE+0x2c) #define ISA_IO_BASE PCI_IO_BASE /* * Environment NVRAM definitions. */ #ifdef ENV_FLASH /* * Definitions for environment in FLASH */ #define NVRAM_START_ENV 0 /* Offset to start of NVRAM data */ #define NVRAM_SIZE_ENV 32766 /* Bytes available */ #elif defined(ENV_MASS) /* * Definitions for environment on mass storage */ #define ENV_DEVICE "/sd0" #define ENV_DEV_OFFS 0x4 /* Start block number */ #define NVRAM_START_ENV 0 /* Offset to start of NVRAM data */ #define NVRAM_SIZE_ENV 4096 /* Bytes available */ #define ENV_DEV_SIZE (NVRAM_SIZE_ENV/512) /* Number of blocks */ #else #define NVRAM_START_ENV 0 #define NVRAM_SIZE_ENV 4096 #endif /* * Additional environment. */ #if defined(AUTOBOOT_DUAL) #define BOOTIMAGE_A "-x -w30 /dev/sd0@0x100 root=/dev/scsibd2" /* image A */ #define BOOTIMAGE_B "-x -w30 /dev/sd0@0x7cf00 root=/dev/scsibd4" /* image B */ #define TGT_DEFENV \ {"bootstate", "A0", "A0 A1 A2 A3 B0 B1 B2 B3"} #endif #if defined(MSP2200_UART) /* * Base UART in MSP2200 (16550 compatible). */ #define MSP2200_SYS_CLK (48000000) /* Hardwired sysclock */ #define COM1_BASE_ADDR (UART_BASE) /* Com 1 */ #define UART_PRESCALE 0x1a #define UART_PRE_REG 2 #define NS16550HZ (MSP2200_SYS_CLK/26) #define nsreg(x) u_int32_t x; #define NSREG(x) ((x) * 4) #define ULDR ldr #define USTR str #else /* * Base UART in IT8712 (16550 compatible). */ #define COM1_BASE_ADDR (LPC_IO_BASE + 0x3f8) /* Com 1 */ #define NS16550HZ (24000000/13) #define nsreg(x) u_int8_t x; #define NSREG(x) x #define ULDR ldrb #define USTR strb #endif /* * MSP2200 specifics. */ /* * Global Registers */ #define GLOBAL_SLEW_RATE_CTRL 0x18 #define GLOBAL_DRIVE_CTRL 0x14 #define GLOBAL_MISC_CTRL 0x28 #define GLOBAL_RESET 0x10 #define GLOBAL_ARBI_CTRL 0x24 #define GLOBAL_ARBI_V 0x00001f10 #define GLOBAL_REMAP_BIT 0x00010000 /* * GPIO Registers */ #define GPIO_BYPASS 0x0c #define GPIO_LPC_PIN 0x10200000 /* GPIO bypass in LPC mode */ #define GPIO_UART_PIN 0x1fe00000 /* GPIO bypass in UART mode */ /* * Dram controller. */ #define DRAM_SDRMR 0x00 /* SDRAM Mode Register */ #define DRAM_SDRTR 0x04 /* SDRAM Timing Register */ #define DRAM_MCR 0x08 /* Memory Control Register */ #define DRAM_SDRTYPE 0x0c /* SDRAM Type Register */ #define DRAM_ARBCR 0x10 /* Arbitration Control Register */ #define DRAM_RDLLCR 0x14 /* Read DLL Control Register */ #define DRAM_WRLLCR 0x18 /* Write DLL Control Register */ #define DRAM_AHBCR 0x0c /* AHB Control Register */ #define SDRMR_DISABLE_DLL 0x80020000 #define SDRAM_SDRTMR_DEFAULT 0x0186d52a #define MCR_DLLTM_ENABLE 0x00000002 #define DRAM_SLEW_DEFAULT 0x00000060 #define DRAM_DRIVE_DEFAULT 0x041400f0 #define SDRAM_SDTMR_DEFAULT 0x0186d52a #ifndef SDRAM_128M #define SDRAM_SDRTYPE_DEFAULT 0x00000002 /* 64 Mb */ #define SDRAM_SIZE_DEFAULT 0x04000000 #else #define SDRAM_SDRTYPE_DEFAULT 0x00000003 /* 128 Mb */ #define SDRAM_SIZE_DEFAULT 0x08000000 #endif /* * RTC */ #define RTC_SEC 0x00 #define RTC_MIN 0x04 #define RTC_HRS 0x08 #define RTC_DAYS 0x0c #define RTC_REC 0x1c #define RTC_CTRL 0x20 /* * Flash registers */ #define FLASH_ACCESS_OFFSET 0x10 #define ACCESS_CONTINUOUS_MODE 0x8000 #endif /* _MSP2200_H_ */