/*
 * Copyright (c) 2001-2005 Opsycon AB  (www.opsycon.se)
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed by Opsycon AB, Sweden.
 *	This product includes software developed by PMC-Sierra, Inc.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */

#include <sys/param.h>
#include <sys/device.h>
#include <sys/systm.h>

#include <sys/malloc.h>

#include <dev/pci/pcivar.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/nppbreg.h>

#include <machine/bus.h>
#include <machine/pio.h>

#include <pmon.h>
#include "usb.h"
#include "uhci.h"
#include "ohci.h"
#include "wd.h"

extern void *pmalloc(size_t);
extern char *getenv(const char *);

/* PCI i/o regions in PCI space */
#define PCI_IO_SPACE_PCI_BASE		0x00000000

/* PCI mem regions in PCI space */
#define PCI_LOCAL_MEM_PCI_BASE	0x00000000	/* CPU Mem accessed from PCI */

/* soft versions of above */
static pcireg_t pci_local_mem_pci_base;

extern int _pcidebug;

extern char hwethadr[6];

struct pci_bus *_pci_bus[16];
int _max_pci_bus = 0;

extern struct tgt_bus_space msp2200_bs_tag;

/*
 * Called to initialise the bridge at the beginning of time
 */
int
_pci_hwinit (initialise, iot, memt)
	int initialise;
	bus_space_tag_t iot;
	bus_space_tag_t memt;
{
	pcireg_t stat;
	struct pci_device *pcidev;
	struct pci_bus *pcibus;
	int i;
	pcitag_t tag;
	pcireg_t reg;

	/*
	 *  PCI and local bus maps 1-1
	 */
	*iot = msp2200_bs_tag;
	*memt = msp2200_bs_tag;
	iot->bs_cookie = (void *)0;
	memt->bs_cookie = (void *)0;

	/*
	 *  Where local memory starts seen from PCI.
	 */
	pci_local_mem_pci_base = PCI_LOCAL_MEM_PCI_BASE;

	if (!initialise) {
		return(0);
	}

	/*
	 *  Allocate and initialize PCI bus heads.
	 */

	/*
	 *  PCI Bus 0
	 */
	pcidev = pmalloc(sizeof(struct pci_device));
	pcibus = pmalloc(sizeof(struct pci_bus));
	if (pcidev == NULL || pcibus == NULL) {
		printf("pci: can't alloc memory. pci not initialized\n");
		return(-1);
	}

	pcidev->pa.pa_bus = 0;
	pcidev->pa.pa_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED;
	pcidev->pa.pa_iot = iot;
	pcidev->pa.pa_memt = memt;
	pcidev->pa.pa_dmat = &bus_dmamap_tag;
	pcidev->bridge.secbus = pcibus;
	_pci_head = pcidev;

	pcibus->minpcimemaddr  = PCI_MEM_SPACE_BASE;
	pcibus->nextpcimemaddr = PCI_MEM_SPACE_BASE + PCI_MEM_SPACE_SIZE;
	pcibus->minpciioaddr   = PCI_IO_SPACE_BASE;
	pcibus->nextpciioaddr  = PCI_IO_SPACE_BASE + PCI_IO_SPACE_SIZE;
	pcibus->pci_mem_base   = PCI_MEM_SPACE_BASE; 	/* Maps 1-1 */
	pcibus->pci_io_base    = PCI_IO_SPACE_BASE; 	/* Maps 1-1 */
	pcibus->max_lat = 255;
	pcibus->fast_b2b = 1;
	pcibus->prefetch = 1;
	pcibus->bandwidth = 4000000;
	pcibus->ndev = 1;
	_pci_bushead = pcibus;
	_pci_bus[_max_pci_bus++] = pcibus;

	/* Set up bridge */
	tag = _pci_make_tag(0, 0, 0);
	reg = _pci_conf_read(tag, PCI_COMMAND_STATUS_REG);
	reg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
	_pci_conf_write(tag, PCI_COMMAND_STATUS_REG, reg);

	reg = 0x00080000;	/* Base 0, size 256M */
	_pci_conf_write(tag, 0x50, reg);
	reg = 0xFF000000;	/* Map away */
	_pci_conf_write(tag, 0x54, reg);
	reg = 0xFF100000;	/* Map away */
	_pci_conf_write(tag, 0x58, reg);


	register_mem((void *)PCI_MEM_SPACE_BASE,
		(void *)PCI_MEM_SPACE_BASE + PCI_MEM_SPACE_SIZE - 1,
		MEM_IO, "PCI memory");
	register_mem((void *)PCI_IO_SPACE_BASE,
		(void *)PCI_IO_SPACE_BASE + PCI_IO_SPACE_SIZE - 1,
		MEM_IO, "PCI I/O");

#if NUSB > 0 && defined(USB_DEBUG)
	if (getenv("usbdebug")) {
		extern int usbdebug, uhcidebug, ohcidebug, umassdebug;
		long val;

		get_rsa(&val, getenv("usbdebug"));
		usbdebug = val & 0xff;
#if NUHCI > 0
		uhcidebug = (val >> 8) 0xff;
#endif
#if NOHCI > 0
		ohcidebug = (val >> 16) & 0xff;
#endif
		if (getenv("umassdebug")) {
			get_rsa(&val, getenv("umassdebug"));
			umassdebug = val;
		}
	}
#endif
	return(1);
}


/*
 * Called to reinitialise the bridge after we've scanned each PCI device
 * and know what is possible. We also set up the interrupt controller
 * routing and level control registers.
 */
void
_pci_hwreinit (void)
{
}

void
_pci_flush (void)
{
}


/*
 *  Map the CPU virtual address of an area of local memory to a PCI
 *  address that can be used by a PCI bus master to access it.
 */
vm_offset_t
_pci_dmamap(va, len)
	vm_offset_t va;
	unsigned int len;
{
	return(pci_local_mem_pci_base + VA_TO_PA (va));
}

/*
 *  Map the PCI address of an area of local memory to a CPU physical
 *  address.
 */
vm_offset_t
_pci_cpumap(pcia, len)
	vm_offset_t pcia;
	unsigned int len;
{
	return PA_TO_VA(pcia - pci_local_mem_pci_base);
}


/*
 *  Make pci tag from bus, device and function data.
 */
pcitag_t
_pci_make_tag(bus, device, function)
	int bus;
	int device;
	int function;
{
	pcitag_t tag;

	tag = (bus << 16) | (device << 11) | (function << 8);
	return(tag);
}

/*
 *  Break up a pci tag to bus, device function components.
 */
void
_pci_break_tag(tag, busp, devicep, functionp)
	pcitag_t tag;
	int *busp;
	int *devicep;
	int *functionp;
{
	if (busp) {
		*busp = (tag >> 16) & 255;
	}
	if (devicep) {
		*devicep = (tag >> 11) & 31;
	}
	if (functionp) {
		*functionp = (tag >> 8) & 7;
	}
}

int
_pci_canscan(pcitag_t tag)
{
	int bus, device, function;

	_pci_break_tag (tag, &bus, &device, &function); 

	/* We don't want to scan and configure the bridge here */
	if(bus == 0 && device == 0) {
		return(0);
	}
	return (1);
}

/*
 *  Read a value form PCI configuration space. Support for 32 bit only.
 */
pcireg_t
_pci_conf_read(pcitag_t tag, int reg)
{
	pcireg_t data, stat;
	u_int32_t adr;
	int bus, device, function;

	if (reg & 3 || reg < 0 || reg > 255) {
		if (_pcidebug >= 1)
			_pci_tagprintf(tag, "_pci_conf_read: bad reg 0x%x\n", reg);
		return ~0;
	}

	_pci_break_tag (tag, &bus, &device, &function); 
	if (bus == 0 && (device > 30 || function > 6))
		return ~0;		/* device out of range */

	adr = (1 << 31) | (bus << 16) | (device << 11) | (function << 8) | reg;

	out32(MSP2200_PCI_CONFIG_ADDR, adr);
	data = in32(MSP2200_PCI_CONFIG_DATA);

	return data;
}

/*
 *  Write a value to PCI configuration space. Support for
 *  all three data sizes (byte, halfword and word) is provided.
 */
void
_pci_conf_write(pcitag_t tag, int reg, pcireg_t data)
{
	u_int32_t adr;
	int bus, device, function;

	if (reg & 3 || reg < 0 || reg > 255) {
		if (_pcidebug >= 1)
			_pci_tagprintf(tag, "_pci_conf_write: bad reg 0x%x\n", reg);
		return;
	}

	_pci_break_tag (tag, &bus, &device, &function);

	if (bus == 0 && (device > 30 || function > 6)) 
		return;		/* device out of range */

	adr = (1 << 31) | (bus << 16) | (device << 11) | (function << 8) | reg;

	out32(MSP2200_PCI_CONFIG_ADDR, adr);
	out32(MSP2200_PCI_CONFIG_DATA, data);
}

/*
 *  Get contents of PCI Mapping register and do any machine
 *  dependent mapping setup.
 */
int
_pci_map_port(tag, reg, port)
	pcitag_t tag;
	int reg;
	unsigned int *port;
{
	pcireg_t address;
    
	if (reg < PCI_MAPREG_START || reg >= PCI_MAPREG_END || (reg & 3)) {
		if (_pcidebug >= 1) {
			_pci_tagprintf(tag, "_pci_map_port: bad request\r\n");
		}
		return -1;
	}
    
	address = _pci_conf_read(tag, reg);
    
	if (PCI_MAPREG_TYPE(address) != PCI_MAPREG_TYPE_IO) {
		if (_pcidebug >= 1) {
			_pci_tagprintf (tag, "_pci_map_port: attempt to i/o map a memory region\r\n");
		}
		return(-1);
	}

	*port = (address & PCI_MAPREG_IO_ADDR_MASK) - PCI_IO_SPACE_PCI_BASE;
	return(0);
}

void *
_pci_map_int(tag, level, func, arg)
	pcitag_t tag;
	int level;
	int (*func) __P((void *));
	void *arg;
{
	pcireg_t data;
	int pin, bus, device;

	data = _pci_conf_read(tag, PCI_INTERRUPT_REG);

	pin = PCI_INTERRUPT_PIN(data);

	if (pin == 0) {
		/* No IRQ used. */
		return NULL;
	}

	if (pin > 4) {
		if (_pcidebug >= 1) {
			_pci_tagprintf (tag, "_pci_map_int: bad interrupt pin %d\r\n", pin);
		}
		return(NULL);
	}


	_pci_break_tag (tag, &bus, &device, NULL);

	if (bus != 0 || device > 5) {
		return(NULL);
	}

	/* XXX need to work this out based on device number etc. */
	_pci_tagprintf(tag, "_pci_map_int: attempt to map device %d pin %c\n", 
		   device, '@' + pin);
	return(NULL);
}

void
pci_sync_cache(p, adr, size, rw)
	void *p;
	vm_offset_t adr;
	size_t size;
	int rw;
{
	CPU_IOFlushDCache(adr, size, rw);
}