#include <machine/endian.h>
/*
 * CP7000-C FPGA Registers 
 */

#ifndef _LOCORE
typedef struct {
    unsigned char revision;	/* Board Assembly Revision */
    unsigned char fpga_rev;	/* FPGA Revision */
    unsigned char fpga_type;	/* Interface Type Register */
    unsigned char reset_stat;	/* Reset Status Register */
    unsigned char board_stat;	/* Board Status Register */
    unsigned char cpci_id;	/* Compact PCI ID Register */
    unsigned char set_reg;	/* LED/SCSI Set Register */
    unsigned char clr_reg;	/* LED/SCSI Clear Register */
    unsigned char reserved;	/* Reserved */
    unsigned char cpu_eeprom;	/* CPU Configuration EEPROM Register */
    unsigned char cpci_intmask;	/* Interrupt Mask Register */
    unsigned char cpci_intstat;	/* Interrupt Status Register */
    unsigned char scsi_intstat; /* SCSI Interrupt Status Register */
    unsigned char uart_intstat; /* UART Interrupt Status Register */
    unsigned char cpci_intset;	/* Interrupt Set Register */
    unsigned char cpci_intclr;	/* Interrupt Clear Register */
} fpgadev;

#endif

#define REVISION	0x0	/* Board Assembly Revision */
#define FPGA_REV	0x1	/* PLD 1 ID */
#define FPGA_TYPE	0x2	/* PLD 2 ID */
#define RESET_STAT	0x3	/* Reset Status Register */
#define BOARD_STAT	0x4	/* Board Status Register */
#define CPCI_ID		0x5	/* Compact PCI ID Register */
#define SET_REG		0x6	/* LED/SCSI Set Register */
#define CLR_REG		0x7	/* LED/SCSI Clear Register */
#define EEPROM		0x9	/* Configuration EEPROM Register */
#define CPCI_INTMASK	0xA	/* Interrupt Mask Register */
#define CPCI_INTSTAT	0xB	/* Interrupt Status Register */
#define SCSI_INTSTAT	0xC	/* SCSI Interrupt Status Register */
#define UART_INTSTAT	0xD	/* UART Interrupt Status Register */
#define CPCI_INTSET	0xE	/* Interrupt Set Register */
#define CPCI_INTCLR	0xF	/* Interrupt Clear Register */

/* Reset Status Register */
#define	RESET_POWER	0x01	/* Power Up Reset */
#define	RESET_BUTTON	0x02	/* Push Button Reset */
#define	RESET_CPCI	0x04	/* Compact PCI Reset */
#define	RESET_WDOG	0x08	/* Watchdog Reset */
#define	RESET_SW	0x10	/* Software Reset */

/* Board Status Register */
#define	BOARD_USER	0x80	/* User Jumper Installed */
#define	BOARD_FWRITE	0x40	/* Flash Write Enable Jumper Installed */
#define	BOARD_RES0	0x20	/* Not used */
#define	BOARD_RES1	0x10	/* Not used */

#define	BOARD_L3_NONE	0x00	/* No L3 Cache */
#define	BOARD_L3_2MB	0x04	/* 2MB L3 Cache */
#define	BOARD_L3_4MB	0x08	/* 4MB L3 Cache */
#define	BOARD_L3_8MB	0x0c	/* 8MB L3 Cache */
#define	BOARD_L3_MASK	0x0c	/* Mask bits */

#define BOARD_RAM_1GB	0x00	/* 1GB DRAM */	
#define BOARD_RAM_128MB	0x01	/* 128MB DRAM */	
#define BOARD_RAM_256MB	0x02	/* 256MB DRAM */	
#define BOARD_RAM_512MB	0x03	/* 512MB DRAM */	
#define BOARD_RAM_MASK	0x03	/* Mask bits */	

/* Compact PCI ID Register */
#define	CPCI_PCI_PRES	0x40	/* PCI Is Present */
#define	CPCI_SSLOT	0x20	/* CPCI System Slot */
#define	CPCI_ADDR_MASK	0x1f	/* Mask bit for Geographical Address */

/* CPU Configuration EEPROM */
#define	EEPROM_CSEL	0x01	/* EEPROM Chip Select */
#define	EEPROM_CLK	0x02	/* EEPROM Clock */
#define	EEPROM_DAT_OUT	0x04	/* EEPROM Data Output */
#define	EEPROM_DAT_IN	0x08	/* EEPROM Data Input */
#define	EEPROM_STROBE	0x10	/* EEPROM Read Strobe */

/* UART Interrupt Status Register */
#define UART_INTSTAT_COM1	0x40	/* UART 1 */
#define UART_INTSTAT_COM2	0x80	/* UART 2 */

/* SCSI Interrupt Status Register */
#define SCSI_INTSTAT_A		0x40	/* SCSI 1 */
#define SCSI_INTSTAT_B		0x80	/* SCSI 2 */

/* CPCI Interrupt Mask Register */
#define	CPCI_INTMASK_INTA	0x01	/* CompactPCI INTA# Mask */
#define	CPCI_INTMASK_INTB	0x02	/* CompactPCI INTB# Mask */
#define	CPCI_INTMASK_INTC	0x04	/* CompactPCI INTC# Mask */
#define	CPCI_INTMASK_INTD	0x08	/* CompactPCI INTD# Mask */
#define	CPCI_INTMASK_BRIDGE	0x10	/* I21554/5 Secondary Interrupt Mask */
#define	CPCI_INTMASK_ENUM	0x20	/* CompactPCI ENUM# Mask */
#define	CPCI_INTMASK_DEG	0x40	/* CompactPCI DEG# Mask */
#define	CPCI_INTMASK_FAL	0x80	/* CompactPCI FAL# Mask */

/* CPCI Interrupt Status Register */
#define	INTSTAT_INTA	INTMASK_INTA	/* CompactPCI INTA# Status */
#define	INTSTAT_INTB	INTMASK_INTB	/* CompactPCI INTB# Status */
#define	INTSTAT_INTC	INTMASK_INTC	/* CompactPCI INTC# Status */
#define	INTSTAT_INTD	INTMASK_INTD	/* CompactPCI INTD# Status */
#define	INTSTAT_BRIDGE	INTMASK_BRIDGE	/* I21554/5 Secondary Interrupt Stat */
#define	INTSTAT_ENUM	INTMASK_ENUM	/* CompactPCI ENUM# Status */
#define	INTSTAT_DEG	INTMASK_DEG	/* CompactPCI DEG# Status */
#define	INTSTAT_FAL	INTMASK_FAL	/* CompactPCI FAL# Status */

/* CPCI Interrupt Set */
#define	INTSET_INTA	INTMASK_INTA	/* CompactPCI INTA# Set */
#define	INTSET_INTB	INTMASK_INTB	/* CompactPCI INTB# Set */
#define	INTSET_INTC	INTMASK_INTC	/* CompactPCI INTC# Set */
#define	INTSET_INTD	INTMASK_INTD	/* CompactPCI INTD# Set */

/* CPCI Interrupt Clear Register */
#define	INTCLR_INTA	INTMASK_INTA	/* CompactPCI INTA# Clear */
#define	INTCLR_INTB	INTMASK_INTB	/* CompactPCI INTB# Clear */
#define	INTCLR_INTC	INTMASK_INTC	/* CompactPCI INTC# Clear */
#define	INTCLR_INTD	INTMASK_INTD	/* CompactPCI INTD# Clear */


/*
 * FPGA Address Macros
 */
#define FPGA_BASE_ADDR	PHYS_TO_IOSPACE(0x1c000000)
#define FPGAREG(x)	(FPGA_BASE_ADDR + x)