/*
 *  Copyright 2003
 *  Alliance Semiconductor. All rights reserved.
 *  
 *  This software is furnished under license and may be used and 
 *  copied only in accordance with the following terms and 
 *  conditions.  Subject to these conditions, you may download, 
 *  copy, install, use, modify and distribute modified or unmodified 
 *  copies of this software in source and/or binary form.  No title 
 *  or ownership is transferred hereby.
 *  
 *  1) Any source code used, modified or distributed must reproduce 
 *     and retain this copyright notice and list of conditions as 
 *     they appear in the source file.
 *  
 *  2) No right is granted to use any trade name, trademark, or 
 *     logo of Alliance Semiconductor Corporation. Neither the "Alliance
 *     Semiconductor" name nor any trademark or logo of Alliance 
 *     Corporation may be used to endorse or promote products 
 *     derived from this software without the prior written 
 *     permission of Alliance Semiconductor .
 *  
 *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
 *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 
 *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
 *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 
 *     SHALL ALLIANCE BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 
 *     PARTICULAR, ALLIANCE SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 
 *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 
 *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 
 *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 
 *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 
 *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 
 *     THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef _HTREG_H_
#define _HTREG_H_

/*
 * Additional HT capability register definitions and macros.
 * Based on the HT Revison 1.05 specification.
 *
 * Note: Register and field definitions assume 32-bit register accesses.
 */

#define HT_BIT(a)                     (0x01<<(a))
#define HT_MASK(offset,width)         (((1<<(width))-1)<<(offset))
#define HT_BMASK(offset)              (0x1<<(offset))
#define HT_GET(data,offset,width)     (((data)>>(offset)) & ((0x1<<(width))-1))
#define HT_BGET(data,offset)          HT_GET(data,offset,1)
#define HT_CLR(data,offset,width)     ((data) & ~HT_MASK(offset,width))
#define HT_BCLR(data,offset)          ((data) & ~HT_BIT(offset))
#define HT_SET(data,offset,width,val) (HT_CLR(data,offset,width) | ((val)<<(offset)))
#define HT_BSET(data,offset,val)      (HT_BCLR(data,offset) | ((val)<<(offset)))
#define HT_MIN(a,b)                   ((a<b) ? a : b)
#define HT_MAX(a,b)                   ((a>b) ? a : b)

/*
 * HT Capability registers (identified by offsets within the capability)
 */
#ifndef PCI_CAP_ID_LDT
#define PCI_CAP_ID_LDT                          0x8
#endif

#define HT_CAP_BASE           	0x00
#define HT_CAP_ID_OFFSET      	0x00
#define HT_CAP_PTR_OFFSET     	0x08
#define HT_CAP_CMD_OFFSET     	0x10
#define HT_CAP_ID_WIDTH       	8 
#define HT_CAP_PTR_WIDTH      	8 
#define HT_CAP_CMD_WIDTH      	16 
#define HT_CAP_ID(cmd)  	HT_GET(cmd, HT_CAP_ID_OFFSET, HT_CAP_ID_WIDTH)
#define HT_CAP_PTR(cmd) 	HT_GET(cmd, HT_CAP_PTR_OFFSET, HT_CAP_PTR_WIDTH)
#define HT_CAP_CMD(cmd) 	HT_GET(cmd, HT_CAP_CMD_OFFSET, HT_CAP_CMD_WIDTH)

/*
 *
 * Primary/Secondary Interface Capability Block Register Definitions
 * HT1.05 Spec. Section 7.5
 *
 */

/* Slave/Primary Interface Block Register Definitions */
/* HT1.05 Spec. Section 7.5 Table 39 */
#define HT_PRI_CAP_BASE                             0x00
#define HT_PRI_LNK_CTRL0_REG                        0x04
#define HT_PRI_LNK_CTRL1_REG                        0x08
#define HT_PRI_REV_ID_REG                           0x0C
#define HT_PRI_FEATURE_REG                          0x10
#define HT_PRI_ENUM_SCRATCH_REG                     0x14
#define HT_PRI_MEM_BASE_UPPER_REG                   0x18

/* Host/Secondary Interface Block Register Definitions */
/* HT1.05 Spec. Section 7.5 Table 39 */
#define HT_SEC_CAP_BASE                          0x00
#define HT_SEC_LNK_CTRL_REG                      0x04
#define HT_SEC_REV_ID_REG                        0x08
#define HT_SEC_FEATURE_REG                       0x0C
#define HT_SEC_ENUM_SCRATCH_REG                  0x10
#define HT_SEC_MEM_BASE_UPPER_REG                0x14

#define HT_LNK_FREQ_ERR_REG                      0x0C

/* Register Bit Definitions - Based on 32bit access */

/* HT Primary command register bit offset definitions */
/* HT1.05 Spec. Section 7.5.3 */
#define HT_CMD_UID_OFFSET                        0x10 
#define HT_CMD_UNIT_CNT_OFFSET                   0x15 
#define HT_CMD_MASTER_HOST_OFFSET                0x1A
#define HT_CMD_DEF_DIR_OFFSET                    0x1B
#define HT_CMD_DROP_ON_UNINIT_OFFSET             0x1C
/* define Masks for fields longer than 1 bit */
#define HT_CMD_UID_WIDTH                         5 
#define HT_CMD_UNIT_CNT_WIDTH                    5 
/* application interface macros */
#define HT_UID(cmd)             HT_GET(cmd, HT_CMD_UID_OFFSET, HT_CMD_UID_WIDTH)
#define HT_UNIT_CNT(cmd)        HT_GET(cmd, HT_CMD_UNIT_CNT_OFFSET, HT_CMD_UNIT_CNT_WIDTH)

#define HT_GET(data,offset,width)     (((data)>>(offset)) & ((0x1<<(width))-1))

#define HT_MASTER_HOST(cmd)     HT_BGET(cmd, HT_CMD_MASTER_HOST_OFFSET)
#define HT_SET_UID(cmd,uid)     HT_SET(cmd, HT_CMD_UID_OFFSET, HT_CMD_UID_WIDTH, uid)

/* HT Secondary command register bit offset definitions */
/* HT1.05 Spec. Section 7.5.3 */
#define HT_CMD_WARM_RESET_OFFSET                 0x10
#define HT_CMD_DBL_ENDED_OFFSET                  0x11
#define HT_CMD_DEVICE_NUM_OFFSET                 0x12 
#define HT_CMD_CHAIN_SIDE_OFFSET                 0x17
#define HT_CMD_HOST_SIDE_OFFSET                  0x18
#define HT_CMD_ACT_AS_SLAVE_OFFSET               0x1A
#define HT_CMD_INB_EOC_ERR_OFFSET                0x1B
/* define Masks for fields longer than 1 bit */
#define HT_CMD_DEVICE_NUM_WIDTH                  5 
/* application interface macros */
#define HT_DEVICE_NUM(cmd)       HT_GET(cmd, HT_CMD_DEVICE_NUM_OFFSET, HT_CMD_DEVICE_NUM_WIDTH)

/* Command Register Capability Type Encoding */
/* HT1.05 Spec. Section 7.5 Table 42 */

/* first 3 bits of the Command field are used to determine host/slave HT capability type */
#define HT_CAP_TYPE_WIDTH                       3 
#define HT_CAP_TYPE_OFFSET                      0x1D
#define HT_CAP_TYPE_SLAVE                       0x0
#define HT_CAP_TYPE_PRI                         0x0
#define HT_CAP_TYPE_HOST                        0x1
#define HT_CAP_TYPE_SEC                         0x1
#define HT_CAP_TYPE(cmd)      HT_GET(cmd, HT_CAP_TYPE_OFFSET, HT_CAP_TYPE_WIDTH)

/* first 5 bits of the Command are used for all other HT Capabilities */
#define HT_CAP_TYPE2_WIDTH                      5 
#define HT_CAP_TYPE2_OFFSET                     0x1B
#define HT_CAP_TYPE2_SLAVE                      0x00
#define HT_CAP_TYPE2_HOST                       0x04
#define HT_CAP_TYPE2_SWITCH                     0x08
#define HT_CAP_TYPE2_INT_DISC                   0x10
#define HT_CAP_TYPE2_REV_ID                     0x11
#define HT_CAP_TYPE2_UID_CLUMP                  0x12
#define HT_CAP_TYPE2_EXT_CFG_ACCESS             0x13
#define HT_CAP_TYPE2_ADDR_REMAP                 0x14
#define HT_CAP_TYPE2(cmd)     HT_GET(cmd, HT_CAP_TYPE2_OFFSET, HT_CAP_TYPE2_WIDTH)


/* Link Control & Configuration Register  */
/* HT1.05 Spec. Section 7.5.4 */
#define HT_LNKCTRL_CFIE                         0x01
#define HT_LNKCTRL_CST                          0x02
#define HT_LNKCTRL_CFE                          0x03
#define HT_LNKCTRL_LKFAIL                       0x04
#define HT_LNKCTRL_INIT                         0x05
#define HT_LNKCTRL_EOC                          0x06
#define HT_LNKCTRL_TXOFF                        0x07
#define HT_LNKCTRL_CRCERROR                     0x08
#define HT_LNKCTRL_ISOCEN                       0x0C
#define HT_LNKCTRL_LSEN                         0x0D
#define HT_LNKCTRL_EXTCTL                       0x0E
#define HT_LNKCTRL_64B                          0x0F
#define HT_LNKCTRL_CRCERROR_WIDTH               4 

/* HT1.05 Spec. Section 7.5.5 */
#define HT_LNKCFG_MAXWIDTH_IN_OFFSET            0x10
#define HT_LNKCFG_DWFC_IN_OFFSET                0x13
#define HT_LNKCFG_MAXWIDTH_OUT_OFFSET           0x14
#define HT_LNKCFG_DWFC_OUT_OFFSET               0x17
#define HT_LNKCFG_LNKWIDTH_IN_OFFSET            0x18
#define HT_LNKCFG_DWFC_IN_EN_OFFSET             0x1B
#define HT_LNKCFG_LNKWIDTH_OUT_OFFSET           0x1C
#define HT_LNKCFG_DWFC_OUT_EN_OFFSET            0x1F
#define HT_LNKCFG_WIDTH_WIDTH                   3 
#define HT_LNKCFG_WIDTH_2BITS                   0x04
#define HT_LNKCFG_WIDTH_4BITS                   0x05
#define HT_LNKCFG_WIDTH_8BITS                   0x00
#define HT_LNKCFG_WIDTH_16BITS                  0x01
#define HT_LNKCFG_WIDTH_32BITS                  0x03

#define HT_LNKWIDTH_IN(cmd)     HT_GET(cmd, HT_LNKCFG_LNKWIDTH_IN_OFFSET, HT_LNKCFG_WIDTH_WIDTH)
#define HT_LNKWIDTH_OUT(cmd)    HT_GET(cmd, HT_LNKCFG_LNKWIDTH_OUT_OFFSET, HT_LNKCFG_WIDTH_WIDTH)
#define HT_MAXWIDTH_IN(cmd)     HT_GET(cmd, HT_LNKCFG_MAXWIDTH_IN_OFFSET, HT_LNKCFG_WIDTH_WIDTH)
#define HT_MAXWIDTH_OUT(cmd)    HT_GET(cmd, HT_LNKCFG_MAXWIDTH_OUT_OFFSET, HT_LNKCFG_WIDTH_WIDTH)

/* Revision ID Register */
/* HT1.05 Spec. Section 7.5.6 */
#define HT_REVID_OFFSET                         0x00
#define HT_REVID_WIDTH                             8 
#define HT_REVID_MINOR_OFFSET                   0x00
#define HT_REVID_MAJOR_OFFSET                   0x04
#define HT_REVID_MINOR_WIDTH                       4 
#define HT_REVID(cmd)           HT_GET(cmd, HT_REVID_OFFSET, HT_REVID_WIDTH)

/* Link Frequency Register */
/* HT1.05 Spec. Section 7.5.7 */
#define HT_LNKFREQ_OFFSET                       0x08
#define HT_LNKFREQ_200MHZ                       0x0
#define HT_LNKFREQ_300MHZ                       0x1
#define HT_LNKFREQ_400MHZ                       0x2
#define HT_LNKFREQ_500MHZ                       0x3
#define HT_LNKFREQ_600MHZ                       0x4
#define HT_LNKFREQ_800MHZ                       0x5
#define HT_LNKFREQ_1000MHZ                      0x6
#define HT_LNKFREQ_WIDTH                         4 
#define HT_LNKFREQ(csr)          HT_GET(csr, HT_LNKFREQ_OFFSET, HT_LNKFREQ_WIDTH)
#define HT_LNKFREQ_SET(csr,freq) HT_SET(csr, HT_LNKFREQ_OFFSET, HT_LNKFREQ_WIDTH, freq)

/* Link Error Register */
/* HT1.05 Spec. Section 7.5.8 */
#define HT_LNKERR_OFFSET                       0x0C
#define HT_LNKERR_PROTOCOL                     0x4
#define HT_LNKERR_OVERFLOW                     0x5
#define HT_LNKERR_EOC                          0x6
#define HT_LNKERR_CTLTO                        0x7
#define HT_LNKERR_WIDTH                         4
#define HT_LNKERR(csr)         HT_GET(csr,HT_LNKERR_OFFSET,HT_LNKERR_WIDTH)


/* Link Frequency Capability Register */
/* HT1.05 Spec. Section 7.5.9 */
#define HT_LNKFREQCAP_OFFSET                  0x10
#define HT_LNKFREQCAP_WIDTH                   16
#define HT_LNKFREQCAP(csr)     HT_GET(csr,HT_LNKFREQCAP_OFFSET,HT_LNKFREQCAP_WIDTH)

/* Feature Capability Register */
/* HT1.05 Spec. Section 7.5.10 */
#define HT_FEATURE_OFFSET                      0x0
#define HT_FEATURE_ISOC                         0x0                    
#define HT_FEATURE_LDTSTOP                      0x1
#define HT_FEATURE_CRC_TEST                     0x2
#define HT_FEATURE_EXT_CTL_TIME                 0x3
#define HT_FEATURE_64BIT_ADDR                   0x4
#define HT_FEATURE_UID_REORDER_DIS              0x5
#define HT_FEATURE_RESERVED                     0x6
#define HT_FEATURE_EXT_REG_SET                  0x8
#define HT_FEATURE_UPSTR_CFG_ENB                0x9
#define HT_FEATURE_PRI_WIDTH                   8        
#define HT_FEATURE_SEC_WIDTH                   16   
#define HT_FEATURE_PRI(csr)    HT_GET(csr, HT_FEATURE_PRI_OFFSET, HT_FEATURE_WIDTH)
#define HT_FEATURE_SEC(csr)    HT_GET(csr, HT_FEATURE_SEC_OFFSET, HT_FEATURE_WIDTH)     

/* Enumeration Scratchpad Register */
/* HT1.05 Spec. Section 7.5.11 */
#define HT_ENUM_SCRATCH_WIDTH                     16

/* Error Handling Register */
/* HT1.05 Spec. Section 7.5.12 */
#define HT_ERR_HANDLE_OFFSET                    0x16
#define HT_ERR_HANDLE_PROT_FLOOD                 0x0
#define HT_ERR_HANDLE_OVF_FLOOD                  0x1
#define HT_ERR_HANDLE_PROT_FATAL                 0x2
#define HT_ERR_HANDLE_OVF_FATAL                  0x3
#define HT_ERR_HANDLE_EOC_FATAL                  0x4
#define HT_ERR_HANDLE_RESP_FATAL                 0x5
#define HT_ERR_HANDLE_CRC_FATAL                  0x6
#define HT_ERR_HANDLE_SERR_FATAL                 0x7
#define HT_ERR_HANDLE_CHAIN_FAIL                 0x8
#define HT_ERR_HANDLE_RESP_ERROR                 0x9
#define HT_ERR_HANDLE_PROT_NONFATAL              0xA
#define HT_ERR_HANDLE_OVF_NONFATAL               0xB
#define HT_ERR_HANDLE_EOC_NONFATAL               0xC
#define HT_ERR_HANDLE_RESP_NONFATAL              0xD
#define HT_ERR_HANDLE_CRC_NONFATAL               0xE
#define HT_ERR_HANDLE_SERR_NONFATAL              0xF
#define HT_ERR_HANDLE_WIDTH                      16

/* Memory Base Upper Register */
/* HT1.05 Spec. Section 7.5.13 */
#define HT_MEM_BASE_UPPER_OFFSET                 0 
#define HT_MEM_BASE_UPPER_WIDTH                  16

/* Memory Base Limit Register */
/* HT1.05 Spec. Section 7.5.14 */
#define HT_MEM_LIMIT_UPPER_OFFSET                0x8 
#define HT_MEM_LIMIT_UPPER_WIDTH                 16 

/* Memoyr Base Limit Register */
/* HT1.05 Spec. Section 7.5.15 */
#define HT_BUS_NUM_OFFSET                        0x10 
#define HT_BUS_NUM_WIDTH                         16 

/*
 *
 * Interrupt Discovery and Configuration Capability Block Register Definitions 
 * HT1.05 Spec. Section 7.6
 *
 */

/* Interrupt Discovery and Configuration Capability Block */
/* HT1.05 Spec. Section 7.6 Tbl 53. */
#define HT_INTR_CAP_BASE_REG                    0x00
#define HT_INTR_DATAPORT_REG                    0x04

#define HT_INTR_CAP_INDEX_OFFSET                0x10 
#define HT_INTR_CAP_INDEX_WIDTH                 8 

#define HT_INTR_CAP_LAST_INTR_OFFSET            0x10 
#define HT_INTR_CAP_LAST_INTR_WIDTH             8 
#define HT_INTR_CAP_LAST_INTR(val)              HT_GET(val, HT_INTR_CAP_LAST_INTR_OFFSET, HT_INTR_CAP_LAST_INTR_WIDTH)
#define HT_INTR_CAP_INTR_DEF_INDEX(N)           (0x10+2*(N))

/* Interrupt Definitions Register Bit definitions */
/* HT1.05 Spec. Tbl 54. */
/* Lower 32bit definitions */
#define HT_INTR_DEF_MASK_OFFSET                        0x00
#define HT_INTR_DEF_POLARITY_OFFSET                    0x01
#define HT_INTR_DEF_MSG_TYPE_OFFSET                    0x02
#define HT_INTR_DEF_REQ_EOI_OFFSET                     0x05
#define HT_INTR_DEF_HT_INT_OFFSET                      0x18                       

/* Upper 32bit definitions */
#define HT_INTR_DEF_PASSPW_OFFSET                      0x1E
#define HT_INTR_DEF_WAIT_EOI_OFFSET                    0x1F

/* X86 Compatible definitions */
#define HT_INTR_DEF_DM_OFFSET                          0x06
#define HT_INTR_DEF_VECTOR_OFFSET                      0x10
#define HT_INTR_DEF_VECTOR_WIDTH                       8 
#define HT_INTR_DEF_DEST_OFFSET                        0x08
#define HT_INTR_DEF_DEST_WIDTH                         8


#define HT_INTR_DEF_MSG_TYPE_WIDTH                     3
#define HT_INTR_DEF_HT_INT                             0xF8                       
#define HT_INTR_DEF_HT_INT_MASK                        (HT_INTR_DEF_HT_INT<<HT_INTR_DEF_HT_INT_OFFSET)

/* X86 Message Type definitions */
#define HT_INTR_DEF_MT_FIXED                         0
#define HT_INTR_DEF_MT_ARB                           1
#define HT_INTR_DEF_MT_SMI                           2
#define HT_INTR_DEF_MT_NMI                           3
#define HT_INTR_DEF_MT_INIT                          4
#define HT_INTR_DEF_MT_STARTUP                       5
#define HT_INTR_DEF_MT_EXTERN                        6
#define HT_INTR_DEF_MT_EOI                           7

/* Destination Modes */
#define HT_INTR_DEF_DM_PHYSICAL                      0
#define HT_INTR_DEF_DM_LOGICAL                       1

/* Trigger Mode */
#define HT_INTR_DEF_EDGE_TRIGGERED                   0
#define HT_INTR_DEF_LEVEL_TRIGGERED                  1

/* Polarity */
#define HT_INTR_DEF_ACTIVE_HI                        0
#define HT_INTR_DEF_ACTIVE_LO                        1


/* Lower 32bit Interrupt Definition Field Access Macros */ 
#define HT_INTR_DEF_MASK(val)                        HT_BGET(val, HT_INTR_DEF_MASK_OFFSET) 
#define HT_INTR_DEF_POLARITY(val)                    HT_BGET(val, HT_INTR_DEF_POLARITY_OFFSET)
#define HT_INTR_DEF_MSG_TYPE(val)                    HT_GET(val, HT_INTR_DEF_MSG_TYPE_OFFSET, HT_INTR_DEF_MSG_TYPE_WIDTH)
#define HT_INTR_DEF_REQ_EOI(val)                     HT_BGET(val, HT_INTR_DEF_REQ_EOI_OFFSET)                   
#define HT_INTR_DEF_VECTOR(val)                      HT_GET(val, HT_INTR_DEF_VECTOR_OFFSET, HT_INTR_DEF_VECTOR_WIDTH)
#define HT_INTR_DEF_MODE(val)                        HT_BGET(val, HT_INTR_DEF_VECTOR_OFFSET)
#define HT_INTR_DEF_DESTINATION(val)                 HT_GET(val, HT_INTR_DEF_DEST_OFFSET, HT_INTR_DEF_DEST_WIDTH)
#define HT_INTR_DEF_ENABLED(val)                     (HT_INTR_DEF_MASK(val) ^ 0x01)

#define HT_INTR_DEF_ENABLE(val)                      HT_BCLR(val, HT_INTR_DEF_MASK_OFFSET)
#define HT_INTR_DEF_DISABLE(val)                     HT_BSET(val, HT_INTR_DEF_MASK_OFFSET, 1)
#define HT_INTR_DEF_SET_POLARITY(val,pol)            HT_BSET(val, HT_INTR_DEF_POLARITY_OFFSET, pol)                   
#define HT_INTR_DEF_SET_REQ_EOI(val,reoi)            HT_BSET(val, HT_INTR_DEF_REQ_EOI_OFFSET, reoi)                   
#define HT_INTR_DEF_SET_VECT(val,vector)             HT_SET(val, HT_INTR_DEF_VECTOR_OFFSET, HT_INTR_DEF_VECTOR_WIDTH, vector)
#define HT_INTR_DEF_SET_MT(val,mt)                   HT_SET(val, HT_INTR_DEF_MSG_TYPE_OFFSET, HT_INTR_DEF_MSG_TYPE_WIDTH,mt)
#define HT_INTR_DEF_SET_DM(val,dm)                   HT_BSET(val, HT_INTR_DEF_DM_OFFSET, dm)
#define HT_INTR_DEF_SET_DEST(val,dest)               HT_SET(val, HT_INTR_DEF_DEST_OFFSET, HT_INTR_DEF_DEST_WIDTH,dest)
#define HT_INTR_DEF_SET_ACTIVE_HI(val)               HT_INTR_DEF_SET_POLARITY(val, HT_INTR_DEF_ACTIVE_HI) 
#define HT_INTR_DEF_SET_ACTIVE_LO(val)               HT_INTR_DEF_SET_POLARITY(val, HT_INTR_DEF_ACTIVE_LO) 
#define HT_INTR_DEF_SET_EDGE_TRIG(val)               HT_INTR_DEF_SET_REQ_EOI(val, HT_INTR_DEF_EDGE_TRIGGERED) 
#define HT_INTR_DEF_SET_LEVEL_TRIG(val)              HT_INTR_DEF_SET_REQ_EOI(val, HT_INTR_DEF_LEVEL_TRIGGERED) 

/* Upper 32bit Interrupt Definition Field Access Macros */ 
#define HT_INTR_DEF_PASSPW(val)                      HT_BGET(val, HT_INTR_DEF_PASSPW_OFFSET)
#define HT_INTR_DEF_WAIT_EOI(val)                    HT_BGET(val, HT_INTR_DEF_WAIT_EOI_OFFSET)

#define HT_INTR_DEF_SET_PASSPW(val,pp)               HT_BSET(val, HT_INTR_DEF_PASSPW_OFFSET,pp)
#define HT_INTR_DEF_CLR_EOI(val)                     HT_BSET(val, HT_INTR_DEF_WAIT_EOI_OFFSET,1)

/*
 *
 * 40Bit/64Bit Address Remapping cability Block Register Definitions 
 * HT1.05 Spec. Section 7.7 & Section 7.8
 *
 */

/* Address Remapping Capability Block */
/* 40Bit/64Bit Common Definitions */
#define HT_REMAP_NUM_OF_DMA_MAPS_OFFSET         0x10
#define HT_REMAP_NUM_OF_DMA_MAPS_WIDTH          4
#define HT_REMAP_IO_SIZE_OFFSET                 0x14
#define HT_REMAP_IO_SIZE_WIDTH                  5
#define HT_REMAP_MAP_TYPE_OFFSET                0x19
#define HT_REMAP_MAP_TYPE_WIDTH                 2
#define HT_REMAP_MAP_TYPE_40BIT                 0x0
#define HT_REMAP_MAP_TYPE_64BIT                 0x1

#define HT_REMAP_NUM_DMA_MAPS(val)             HT_GET(val, HT_REMAP_NUM_OF_DMA_MAPS_OFFSET, HT_REMAP_NUM_OF_DMA_MAPS_WIDTH)
#define HT_REMAP_IO_SIZE(val)                  HT_GET(val, HT_REMAP_IO_SIZE_OFFSET, HT_REMAP_IO_SIZE_WIDTH)
#define HT_REMAP_MAP_TYPE(val)                 HT_GET(val, HT_REMAP_MAP_TYPE_OFFSET, HT_REMAP_MAP_TYPE_WIDTH)

/* Remap Control Register Bit definitions */
#define HT_REMAP_CTRL_COMPAT                    0x00
#define HT_REMAP_CTRL_NONCHRNT                  0x01
#define HT_REMAP_CTRL_ISOC                      0x02
#define HT_REMAP_CTRL_ENABLE                    0x03


/* 40Bit Address Remapping Capability Block  */
/* HT1.05 Spec. Section 7.7 */
#define HT_REMAP_40BIT_CAP_BASE_REG             0x00
#define HT_REMAP_40BIT_SEC_NONPREF_BASE_REG     0x04
#define HT_REMAP_40BIT_SEC_PREF_BASE_REG        0x08
#define HT_REMAP_40BIT_DMA_PRIM_BASE(N)         (0x08*N+0x04) 
#define HT_REMAP_40BIT_DMA_SEC_LIMIT(N)         (0x08*N+0x08)

#define HT_REMAP_40BIT_CTRL_OFFSET              0x1C
#define HT_REMAP_40BIT_CTRL_MASK                0xF00000000

/* 64Bit Address Remapping Capability Block  */
/* HT1.05 Spec. Section 7.8 */
#define HT_REMAP_64BIT_CAP_BASE_REG             0x00
#define HT_REMAP_64BIT_INDEX_REG                0x04
#define HT_REMAP_64BIT_DATA_LO_REG              0x08
#define HT_REMAP_64BIT_DATA_HI_REG              0x0C

#define HT_REMAP_64BIT_INDEX_WIDTH               6 
#define HT_REMAP_64BIT_INDEX_OFFSET              0 

/* 64Bit Address Remap Indexed Registers */
#define HT_REMAP_64BIT_INDEX_SBNPCTRL           0x00
#define HT_REMAP_64BIT_INDEX_SEC_NPBASE         0x00
#define HT_REMAP_64BIT_INDEX_SBPRECTRL          0x01
#define HT_REMAP_64BIT_INDEX_SEC_BASE           0x01
#define HT_REMAP_64BIT_INDEX_PRI_WINDOW         0x02
#define HT_REMAP_64BIT_INDEX_RESERVED           0x03
#define HT_REMAP_64BIT_INDEX_DMACTRL(N)         (0x04*(N+1))
#define HT_REMAP_64BIT_INDEX_DMA_SEC_BASE(N)    (0x04*(N+1)+1)
#define HT_REMAP_64BIT_INDEX_DMA_SEC_LIMIT(N)   (0x04*(N+1)+2)

/* Revision ID Capability Block */
/* HT1.05 Spec. Section 7.9 */
#define HT_REV_ID_CAP_BASE_REG                  0x0
#define HT_REV_ID_REVISION_OFFSET               0x10
#define HT_REV_ID_REVISION_WIDTH                8 
#define HT_REVISION(data) HT_GET(data, HT_REV_ID_REVISION_OFFSET, HT_REV_ID_REVISION_WIDTH)

/* UnitID Clumping Capability Block */
/* HT1.05 Spec. Section 7.10 */
#define HT_UID_CLUMP_CAP_BASE_REG               0x00
#define HT_UID_CLUMP_SUPPORT_REG                0x04
#define HT_UID_CLUMP_ENABLE_REG                 0x08

/* Extended Cofiguration Space Access Capability Block */
/* HT1.05 Spec. Section 7.11 */
#define HT_EXT_CSR_ACCESS_CAP_BASE_REG          0x00
#define HT_EXT_CSR_ACCESS_REG_REG               0x04
#define HT_EXT_CSR_ACCESS_DATA_REG              0x08
/* TODO: Define extended cfg acess methods. */

/* Switch Capability Block */
/* HT1.05 Spec. Section I.3.3 */
#define HT_SWITCH_CAP_BASE_REG                  0x00
#define HT_SWITCH_PART_MASK_REG                 0x04
#define HT_SWITCH_SWITCH_INFO_REG               0x08
#define HT_SWITCH_PERF_COUNTER_DATA_REG         0x0C
#define HT_SWITCH_BLR_DATA_REG                  0x10
#define HT_SWITCH_SEC_BASE_DATA_REG             0x14
/* Switch Performance Counters Index */
#define HT_SWITCH_PERF_INDEX_P_CMD_RX           0x0
#define HT_SWITCH_PERF_INDEX_NP_CMD_RX          0x1
#define HT_SWITCH_PERF_INDEX_RESP_CMD_RX        0x2
#define HT_SWITCH_PERF_INDEX_P_DW_RX            0x3
#define HT_SWITCH_PERF_INDEX_NP_DW_RX           0x4
#define HT_SWITCH_PERF_INDEX_RESP_DW_RX         0x5
#define HT_SWITCH_PERF_INDEX_P_CMD_TX           0x6
#define HT_SWITCH_PERF_INDEX_NP_CMD_TX          0x7
#define HT_SWITCH_PERF_INDEX_RESP_CMD_TX        0x8
#define HT_SWITCH_PERF_INDEX_P_DW_TX            0x9
#define HT_SWITCH_PERF_INDEX_NP_DW_TX           0xA
#define HT_SWITCH_PERF_INDEX_RESP_DW_TX         0xB
/* Switch Base/Limit Range Register index */
#define HT_SWITCH_BLR_BASE_LO                   0x0
#define HT_SWITCH_BLR_BASE_HI                   0x1
#define HT_SWITCH_BLR_LIMIT_HI                  0x2
#define HT_SWITCH_BLR_LIMIT_LO                  0x3

#endif /* _HTREG_H_ */