/* * Copyright (c) 2005 Opsycon AB (www.opsycon.se) * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Opsycon AB, Sweden. * 4. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ void init_ati(void); void ati_render_char(u_char, int , int, int, int); void ati_scroll(int , int, int); void ati_cursor(int , int, int, int); void ati_dsp_enable(int); /* Chip configuration registers */ #define CONFIG_CNTL 0x00DC /* 0_37 */ #define CONFIG_CHIP_ID 0x00E0 /* 0_38 */ #define CONFIG_STAT0 0x00E4 /* 0_39 */ /* Chip clock control */ #define CLOCK_CNTL 0x0090 /* 0_24 */ #define CLOCK_CNTL_SEL 0x0090 /* 0_24 (alias used with byte write */ #define CLOCK_SEL 0x03 #define CLOCK_CNTL_ADDR 0x0091 /* 0_24 (alias used with byte write */ #define PLL_WR_EN 0x02 #define CLOCK_CNTL_DATA 0x0092 /* 0_24 (alias used with byte write */ #define CLOCK_DIV 0x30 #define CLOCK_DIV1 0x00 #define CLOCK_DIV2 0x10 #define CLOCK_DIV4 0x20 #define CLOCK_STROBE 0x40 /* PLL register indices */ #define MPLL_CNTL 0x00 #define VPLL_CNTL 0x01 #define PLL_REF_DIV 0x02 #define PLL_GEN_CNTL 0x03 #define MCLK_FB_DIV 0x04 #define PLL_VCLK_CNTL 0x05 #define VCLK_POST_DIV 0x06 #define VCLK0_FB_DIV 0x07 #define VCLK1_FB_DIV 0x08 #define VCLK2_FB_DIV 0x09 #define VCLK3_FB_DIV 0x0A #define PLL_EXT_CNTL 0x0B #define DLL_CNTL 0x0C #define DLL1_CNTL 0x0C #define VFC_CNTL 0x0D #define PLL_TEST_CNTL 0x0E #define PLL_TEST_COUNT 0x0F #define LVDS_CNTL0 0x10 #define LVDS_CNTL1 0x11 #define AGP1_CNTL 0x12 #define AGP2_CNTL 0x13 #define DLL2_CNTL 0x14 #define SCLK_FB_DIV 0x15 #define SPLL_CNTL1 0x16 #define SPLL_CNTL2 0x17 #define APLL_STRAPS 0x18 #define EXT_VPLL_CNTL 0x19 #define EXT_VPLL_REF_DIV 0x1A #define EXT_VPLL_FB_DIV 0x1B #define EXT_VPLL_MSB 0x1C #define HTOTAL_CNTL 0x1D #define BYTE_CLK_CNTL 0x1E #define TV_PLL_CNTL1 0x1F #define TV_PLL_CNTL2 0x20 #define TV_PLL_CNTL 0x21 #define EXT_TV_PLL 0x22 #define V2PLL_CNTL 0x23 #define PLL_V2CLK_CNTL 0x24 #define EXT_V2PLL_REF_DIV 0x25 #define EXT_V2PLL_FB_DIV 0x26 #define EXT_V2PLL_MSB 0x27 #define HTOTAL2_CNTL 0x28 #define PLL_YCLK_CNTL 0x29 #define PM_DYN_CLK_CNTL 0x2A /* Fields in PLL registers */ #define PLL_PC_GAIN 0x07 #define PLL_VC_GAIN 0x18 #define PLL_DUTY_CYC 0xE0 #define PLL_OVERRIDE 0x01 #define PLL_MCLK_RST 0x02 #define OSC_EN 0x04 #define EXT_CLK_EN 0x08 #define MCLK_SRC_SEL 0x70 #define EXT_CLK_CNTL 0x80 #define VCLK_SRC_SEL 0x03 #define PLL_VCLK_RST 0x04 #define VCLK_INVERT 0x08 #define VCLK0_POST 0x03 #define VCLK1_POST 0x0C #define VCLK2_POST 0x30 #define VCLK3_POST 0xC0 #define MPLL_GAIN 0xad #define VPLL_GAIN 0xd5 #define GUI_CNTL 0x0578 /* 1_5E */ /* Chip test and debug */ #define HW_DEBUG 0x007C /* 0_1F */ /* Memory Control */ #define EXT_MEM_CNTL 0x00AC /* 0_2B */ #define MEM_CNTL 0x00B0 /* 0_2C */ #define MEM_VGA_WP_SEL 0x00B4 /* 0_2D */ #define MEM_VGA_RP_SEL 0x00B8 /* 0_2E */ /* Chip memory buffer control */ #define DSP_CONFIG 0x0020 /* 0_08 */ #define DSP_ON_OFF 0x0024 /* 0_09 */ #define TIMER_CONFIG 0x0028 /* 0_0A */ #define MEM_BUF_CNTL 0x002C /* 0_0B */ #define MEM_ADDR_CONFIG 0x0034 /* 0_0D */ /* Chip accelerator CRTC */ #define CRTC_H_TOTAL_DISP 0x0000 /* 0_00 */ #define CRTC_H_SYNC_STRT_WID 0x0004 /* 0_01 */ #define CRTC_H_SYNC_STRT 0x0004 #define CRTC_H_SYNC_DLY 0x0005 #define CRTC_H_SYNC_WID 0x0006 #define CRTC_V_TOTAL_DISP 0x0008 /* 0_02 */ #define CRTC_V_TOTAL 0x0008 #define CRTC_V_DISP 0x000A #define CRTC_V_SYNC_STRT_WID 0x000C /* 0_03 */ #define CRTC_V_SYNC_STRT 0x000C #define CRTC_V_SYNC_WID 0x000E #define CRTC_VLINE_CRNT_VLINE 0x0010 /* 0_04 */ #define CRTC_OFF_PITCH 0x0014 /* 0_05 */ #define CRTC_OFFSET 0x0014 #define CRTC_PITCH 0x0016 #define CRTC_INT_CNTL 0x0018 /* 0_06 */ #define CRTC_GEN_CNTL 0x001C /* 0_07 */ #define CRTC_PIX_WIDTH 0x001D #define CRTC_FIFO 0x001E #define CRTC_EXT_DISP 0x001F #define CRTC_EXT_DISP_EN 0x01000000 #define CRTC_ENABLE 0x02000000 #define CRTC_CSYNC_EN 0x00000004 #define CRTC_PIX_WIDTH_8BPP 0x00000200 #define CRTC_PIX_WIDTH_15BPP 0x00000300 #define CRTC_PIX_WIDTH_24BPP 0x00000500 #define CRTC_PIX_WIDTH_32BPP 0x00000600 #define BYTE_ORDER_LSB_TO_MSB 0x1000000 #define HOST_8BPP 0x20000 #define HOST_15BPP 0x30000 #define HOST_16BPP 0x40000 #define HOST_32BPP 0x60000 #define SRC_8BPP 0x200 #define SRC_15BPP 0x300 #define SRC_16BPP 0x400 #define SRC_32BPP 0x600 #define DST_8BPP 0x2 #define DST_15BPP 0x3 #define DST_16BPP 0x4 #define DST_32BPP 0x6 /* Bus Control */ #define BUS_CNTL 0x00A0 /* 0_28 */ /* LCD Control */ #define LCD_INDEX 0x00A4 /* Dword offset 0_29 */ #define LCD_DATA 0x00A8 /* Dword offset 0_2A */ /* DAC Control */ #define DAC_REGS 0x00C0 /* Dword offset 0_30 */ #define DAC_W_INDEX 0x00C0 /* Dword offset 0_30 */ #define DAC_DATA 0x00C1 /* Dword offset 0_30 */ #define DAC_MASK 0x00C2 /* Dword offset 0_30 */ #define DAC_R_INDEX 0x00C3 /* Dword offset 0_30 */ #define DAC_CNTL 0x00C4 /* Dword offset 0_31 */ #define EXT_DAC_REGS 0x00C8 /* Dword offset 0_32 */ /* Test and Debug */ #define GEN_TEST_CNTL 0x00D0 /* Dword offset 0_34 */ /* Custom Macros */ #define CUSTOM_MACRO_CNTL 0x00D4 /* Dword offset 0_35 */ /* General I/O Control */ #define GP_IO 0x0078 /* Dword offset 0_1E */