/* * Copyright (c) 2004 PMC-Sierra, Inc. (www.pmc-sierra.com) * Copyright (c) 2001 Opsycon AB (www.opsycon.se) * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Opsycon AB, Sweden. * 4. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #ifndef _YOSEMITE_H_ #define _YOSEMITE_H_ #include /* * Define top of PMON-land. PMON will not use memory above this * address but leave it alone for applications. */ #define PMON_TOP 0x08000000 /* 128MB */ /* * Device chip select mapping */ #define BOOT_BASE 0xffc00000 #ifdef USE_TSOP_FLASH #define BOOT_SIZE 0x00200000 #else #define BOOT_SIZE 0x00080000 #endif #define FLASH_BASE 0xff000000 #define FLASH_SIZE 0x00c00000 #ifdef RM9200_UART #define UART_BASE RM9000_ETH_BASE + 0x200 #define UART_SIZE 0x00000068 #else #define UART_BASE 0xfd000000 #define UART_SIZE 0x01000000 #endif #define RTC_BASE 0xfc800000 #define RTC_SIZE 0x00800000 #define FPGA_BASE 0xfc000000 #define FPGA_SIZE 0x00800000 /* * Ethernet registers */ #define RM9000_ETH_BASE 0xfe000000 #define RM9000_ETH_SIZE 0x00010000 /* * PCI Bus 0 */ #if 0 #define PCI0_MEM_SPACE_BASE 0xd0000000 #define PCI0_MEM_SPACE_SIZE 0x04000000 #define PCI0_IO_SPACE_BASE 0xe0000000 #define PCI0_IO_SPACE_SIZE 0x01000000 #else #define PCI0_MEM_SPACE_BASE 0xe0000000 #define PCI0_MEM_SPACE_SIZE 0x07000000 #define PCI0_IO_SPACE_BASE 0xe8000000 #define PCI0_IO_SPACE_SIZE 0x01000000 #endif /* * Hypertransport (PCI compliant) */ #define PCI1_MEM_SPACE_BASE 0xe9010000 #define PCI1_MEM_SPACE_SIZE 0x04000000 #define PCI1_IO_SPACE_BASE 0xed010000 #define PCI1_IO_SPACE_SIZE 0x01000000 #define ISA_IO_BASE PCI_IO_BASE /* * Semaphore definitions */ #define RM9000_SEM_HOLD 0x80000000 #define RM9000_SEM_ALIVE 0x40000000 /* * RM9000 on-chip RAM */ #if 0 #define SRAM_BASE 0x1a000000 /* customer legacy, conflict with 512MB memory */ #else #define SRAM_BASE 0xf4000000 #endif #define SRAM_SIZE 0x00002000 /* * Bootrom parameters */ #define BOOTROM_BASE 0xffc0000 #define BOOTROM_SIZE (1024 * 512) /* * Timekeeper/NVRAM (M48T37) */ #define M48T37_RTC_BASE (RTC_BASE + 0x7ff0) #define M48T37_NVRAM_BASE (RTC_BASE) #define NVRAM_ENETADDR (RTC_BASE + 0x7cf2) /* * Device module duart I/O ports */ #ifdef RM9200_UART #define COM1_BASE_ADDR (UART_BASE + 0x08) /* Com 1 */ #define COM2_BASE_ADDR (UART_BASE + 0x38) /* Com 2 */ #define NS16550HZ 25000000 #define nsreg(x) unsigned int x #else #define COM1_BASE_ADDR (UART_BASE + 0x08) /* Com 1 */ #define COM2_BASE_ADDR (UART_BASE + 0x00) /* Com 2 */ #define NS16550HZ 3686400 #define nsreg(x) unsigned char x #endif #define NSREG(x) (x) /* * Macros */ /* OCD registers */ #define OCD_RESET_ADDR PHYS_TO_UNCACHED(0x1b000000) #define OCD_BASE_ADDR 0xfb000000 #define OCD_SIZE 0x4000 #ifndef _LOCORE #define RM9K_WRITE(ofs, data) \ *(volatile u_int32_t *)(OCD_BASE_ADDR+ofs) = data #define RM9K_READ(ofs) \ *(volatile u_int32_t *)(OCD_BASE_ADDR+ofs) /* MAC subsystem */ #define RM9000_GE_BASE_ADDR RM9000_ETH_BASE #define RM9000_GE_READ(offset) \ *(volatile uint32_t *)(RM9000_GE_BASE_ADDR + offset) #define RM9000_GE_WRITE(offset, data) \ *(volatile uint32_t *)(RM9000_GE_BASE_ADDR + offset) = data /* SCMB subsystem (MDIO mode) */ #define PHY_ANEG_TIME_WAIT 30 /* wait time (sec) */ #define RM9000_MDIO_BASE_ADDR RM9000_ETH_BASE #define RM9000_MDIO_READ(offset) \ *(volatile uint32_t *)(RM9000_MDIO_BASE_ADDR + offset) #define RM9000_MDIO_WRITE(offset, data) \ *(volatile uint32_t *)(RM9000_MDIO_BASE_ADDR + offset) = data /* SCMB subsystem (2BI mode) */ #define RM9000_2BI_BASE_ADDR RM9000_ETH_BASE #define RM9000_2BI_READ(offset) \ *(volatile uint32_t *)(RM9000_2BI_BASE_ADDR + offset) #define RM9000_2BI_WRITE(offset, data) \ *(volatile uint32_t *)(RM9000_2BI_BASE_ADDR + offset) = data /* FPGA access */ #define VCCOK 0x01 #define COLDRESET 0x02 #define WDTIMERRESETB 0x04 #define USERSWITCH_S5_6 0x08 #define USERSWITCH_S5_5 0x10 #define USERSWITCH_S5_4 0x20 #define FLASH_WRITE_ENABLE 0x40 #define BE 0x80 #define FPGA_READ(offset) \ *(volatile uint8_t *)(FPGA_BASE + offset) #endif /* * Config stream registers */ #define RM9K_CONF000 0x00d0 #define RM9K_CONF032 0x00d4 #define RM9K_CONF064 0x00d8 #define RM9K_CONF096 0x00dc #define RM9K_CONF128 0x00e0 #define RM9K_CONF160 0x00e4 #define RM9K_CONF192 0x00e8 #define RM9K_CONF224 0x00ec /* * Define how to test for non-dmaable address range */ #define IS_DMA_ABLE(addr) \ (addr >= 0x90000000) #endif /* _YOSEMITE_H_ */